lm27213mtd National Semiconductor Corporation, lm27213mtd Datasheet - Page 19

• Manufacturer Part Number: lm27213mtd
• Description: Single Phase Hysteretic Buck Controller
• Manufacturer: National Semiconductor Corporation

Layout Guidelines
Keep the switch node connection between the two FETs and
the inductor as short and wide as possible. The inductor
should be located very close to the FETs. The inductor
should then flow in to the sense resistor that needs to be
immediately adjacent to the processor decoupling capaci-
tors.
The LM27213 needs to be located relatively close to the
FETs to minimize the gate drive lengths. Also, route the
high-side gate signal (pin 2) and the SW pin (3) parallel to
and very close to each other to minimize the inductance of
the loop enclosed. These traces should be at least 15 mils
wide. The connections to the current sense resistor must be
made as Kelvin connections. Again, route these two traces in
parallel if possible to minimize noise susceptibility. The
sense pin (16) is best connected to the core voltage near the
center of the CPU socket, but will in all likelihood work
correctly if connected at the bypass capacitors located
around the periphery of the CPU socket. This line is the
source of output voltage information for the over voltage
protection circuit and power good comparators.
Probably the most critical consideration for the controller is
grounding. There are several ground-referenced pins that
need to be treated quite differently. A good practice is to tie
the power ground pin (45) to the main power plane with a
single via. This pin is the ground connection for the gate
drive and as such will carry very large pulse currents. The
bypass capacitor for DVDD should connect very close to this
ground connection if at all possible. DGND (13) is not par-
ticularly critical and should tie to the main ground plane as
well. It only carries the return currents for the digital portions
of the controller, which are not very large. The SGND pin
(23) is the most critical and should also tie to the plane with
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a separate via close to PGND or directly to the PGND pin
with a very short trace. One grounding option is to define a
signal ground plane that connects to ground through this
point only and resides under and around the IC. An alterna-
tive is to daisy chain a ground trace around the controller to
pick up all the signal ground referenced components while
maintaining only a single connection to the ground plane at
the SGND pin. If doing the later and not defining signal
ground as a separate net, it will not be possible to use vias to
connect to other layers unless your board layout package
has the ability to isolate these vias from the ground plane.
Keeping the signal ground separate from the system ground
plane ensures that signal ground is “quiet” relative to all
internal signals in the controller. The main ground plane is
usually a very noisy environment and not the absolute zero
volt reference it tends to be thought of. Pains should be
taken at every opportunity to ensure that sources of large
pulse currents into the ground plane are bypassed as well as
possible to minimize the disturbances to the ground plane.
Under no circumstances should the controller be grounded
at a point between the low-side FET source connection and
the input capacitor ground connection point. This is a very
noisy area.
Pin 5, SRCK, is the low-side FET source Kelvin connection
and as the name implies needs to be connected directly to
the low side FET source pads. This pin is used as the
reference potential for the diode emulator circuit. If not con-
nected correctly, the supply will behave erratically at light
loads. The correct connection for SRCK is to tie the pin to
one of the vias connecting the low-side FET source to the
internal ground plane on an internal layer or the back side of
the board. The trace need not be wide. A 10mil trace is
adequate, as this line carries essentially no current.
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