lm27213mtd National Semiconductor Corporation, lm27213mtd Datasheet - Page 18

• Manufacturer Part Number: lm27213mtd
• Description: Single Phase Hysteretic Buck Controller
• Manufacturer: National Semiconductor Corporation

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Component Selection
So for a design that must operate at a steady state load
current of 12A, with 1.4V out and 8V in, the RMS input ripple
current would be about 37% of 12A or 4.4A RMS. A sufficient
number of capacitors must be connected in parallel to
handle this current. For capacitors rated at 1.5A each, a
minimum of 3 would be required. If it’s desired to add enough
bulk capacitance to control the input’s low frequency ripple
voltage, the characteristic impedance of the input power
source must be well understood.
Bypassing Considerations
The LM27213 should have its supply pin (24) well bypassed.
Generally a 1µF capacitor connected between the Vdd pin
and the SGND pin (23), should be adequate. It’s a good idea
to add a resistor of about 10Ω in series with the input source
to provide some decoupling from noise on the 5V rail. The
LM27213’s own gate drive pulse currents can corrupt the 5V
rail enough to cause problems without this filter. There also
needs to be a 1µF or larger ceramic capacitor connected
between the driver supply pin PVDD (48) and PGND (45).
The bypass capacitors should be located very close to the
pins to provide a low inductance path. This is particularly
important for the PVDD bypass. This capacitor must supply
all of the low-side gate drive pulse currents as well as the
charging current for the high-side bootstrap capacitor. It’s
also a good idea to install a 0.1µF capacitor between the
VREF pin (11) and SGND. In addition, there should be small
filter capacitors connected between the ILIM and ILIMREF
pins and the CMP and CMPREF pins. Typically, a 1200pF
capacitor will prove adequate for this purpose.
Current Sense Resistor
The maximum value allowed for the current sense resistor is
a value equal to the desired load line slope. Increasing
beyond this value will make the load line excessively steep
with no way to reduce the slope. Lower values are permis-
sible and values as low as 1mΩ have been used success-
fully. The regulator will have a tendency to exhibit excessive
amounts of pulse jitter if the sense resistor is too small since
the current sense signal is reduced as well. One way to
mitigate this problem is to add a little filtering to the load line
setting resistor R2 in Figure 3. A typical time constant to
FIGURE 4. RMS Input Ripple Current as a Percentage
of DC Output Current
(Continued)
20154327
18
shoot for is approximately 500ns. So for R2 = 100Ω, some-
thing around a 4700pF capacitor should prove helpful. If this
capacitor is made too large the result will be large overshoot
and undershoot in the response to load transients. See the
section below on load line setting for more information about
choosing these resistors.
Load Line Setting Resistors
Resistors R1, R2, and the current sense resistor (see Figure
2) are used to control the slope of the load line. In the
simplest configuration R1 = 0 ohms and R2 is omitted. In this
case the load line is nominally equal to the current sense
resistor value. For relatively low current designs this configu-
ration can work acceptably well. At higher current levels the
DC drop across the power planes may well contribute an
excessive error since the distribution path between the
sense resistor and the load is effectively in series with the
current sense resistor, and therefore, will steepen the load
line. For designs with relatively steep load lines (3 mΩ) the
power dissipation is also excessive at high currents. The
solution is to lower the sense resistor value and add the R1,
R2 divider to synthesize a steeper slope. The load line is
calculated from:
Since the power plane resistance will increase the load line
by an amount that’s nearly impossible to estimate accurately,
the simplest approach is to install the values calculated for
the ideal, lossless power path, and run the circuit. Record
the no load and full load output voltage and calculate the
load line impedance.
Where:
V
V
And I
Use this information along with the installed values of R1 and
R2 to calculate the effective sense resistor value:
Now using this value of sense resistor, recalculate a new
value for R1:
Installing these values for R1 and R2 should yield a nearly
perfect load line.
Layout Guidelines
As is true for any high-current power supply design, care
needs to be taken when doing an LM27213 layout. As a
general rule, it makes the most sense to start the layout by
placing the power path components to connect in a logical
power flow. The input ceramic capacitors should be con-
nected as close as physically possible to the source of the
low side FET and the drain of the high-side FET. The loop
area enclosed by the input capacitors and FETs needs to be
minimized to control ringing and optimize the switch rise and
fall times. A good practice is to connect the FETs on the top
side of the board with the bypass capacitors located imme-
diately below on the back side. The capacitors’ ground pads
should be located directly beneath the low-side FET’s source
pad and a collection of vias used to hook the two together
and at the same time tie to the internal ground plane. Figure
on allowing one amp of load current per via if the hole
diameter is less than 15 mils and two Amps per via if greater
than 20 mils. More vias are almost always better than fewer.
0
full
is the no load output voltage
is the full load output voltage
full
is the full load current
LL = R
R1 = R2(LL/R
R
LL = (V
se
= LL/(1+R1/R2)
s
0
x (1+R1/R2)
– V
full
se
)/I
–1)
full