tza3054a NXP Semiconductors, tza3054a Datasheet - Page 10

• Manufacturer Part Number: tza3054a
• Description: 100 Mbits/s To 3.2 Gbits/s A-rate Tm Limiting Amplifier
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13466
Objective data sheet
8.5.1 JAM
If the I
output buffer can be selected from two fixed values. By applying a HIGH level to pin LVL
1570 mV (p-p, differential) is selected (this is the default mode after power-up due to the
internal pull-up resistor). By applying a LOW level to pin LVL 500 mV (p-p, differential) is
selected.
As part of the ACE functionality, the slew rate of the output is adjusted automatically for
any bit rate to approximately 10 % of the corresponding Unit Interval time, by a built-in
slew rate control loop. The slew rate control loop eases ElectroMagnetic Compatibility
(EMC) and ElectroMagnetic Interference (EMI) compliance of the final module design, as
well as dramatic power saving, especially for lower bit rates. To estimate the power
dissipation use
output supply current as a function of output voltage swing. By adding both independent
currents the total supply current can be calculated.
The automatic slew rate adjustment can be overruled by manual setting of the output
stage via the I
signals; see the
The RF output can be forced into the logic 0 state by applying a LOW-level to the JAM pin
(pin JAM is active LOW). Hence in the event of a loss of signal situation, the output can be
jammed to suppress the amplified noise from the optical front-end. The JAM pin has an
internal pull-up, to prevent jamming of the output if the JAM pin is not connected.
If CMOS compatibility is required, pin JAM can be programmed to be active HIGH with
I
Jamming can also be done via the I
function and I
JAM can also be programmed to work automatically when loss of signal occurs. This can
be done by connection pin LOS to pin JAM directly or with I
register RFLVL; 13h).
2
Fig 10. CMOS input configuration.
C-bus bit JAMPOL (I
2
C-bus setting for the output level is set to pin selection, the signal amplitude of the
2
2
C-bus bit JAM to actually jam the output (I
C-bus. This may be required in the event of non-randomized or burst-mode
Figure 17
Section
CMOS
V
input
GND
CCO
2
Rev. 01 — 12 August 2004
C-bus register RFLVL; 13h).
8.6.
Core supply current as a function of bit rate, and
ESD CLAMP
2
C-bus, using I
100 Mbit/s to 3.2 Gbit/s A-rate
SECONDARY
ESD CLAMP
2
C-bus bit I2CJAM to enable this
2
C-bus register RFLVL; 13h).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
2
C-bus bit AUTOJAM (I
001aab372
TZA3054A
limiting amplifier
Figure 18
2
10 of 32
C-bus
RF