tza3005 NXP Semiconductors, tza3005 Datasheet - Page 11

• Manufacturer Part Number: tza3005
• Description: Sdh/sonet Stm1/oc3 And Stm4/oc12 Transceiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
edge of RXPCLK. When a 4-bit bus width is selected,
TXPD7 is the most significant bit and bit 4 is the least
significant bit.
19 MHz clock output (19MHzO)
This is a 19 MHz CMOS clock output from the clock
synthesizer. It should be connected to the reference clock
input of the external clock recovery function (such as the
TZA3004).
Frame Pulse (FP)
This CMOS output detects frame boundaries in the
incoming data stream (RXSD). When framing pattern
detection is enabled (see Section “Out-Of-Frame (OOF)”),
FP goes HIGH for one cycle of RXPCLK when a 48-bit
sequence matching the framing pattern is detected on the
RXSD inputs. When framing pattern detection is disabled,
FP goes HIGH when, after byte alignment, the incoming
data stream matches the framing pattern. FP is updated on
the falling edge of RXPCLK.
Parallel output clock (RXPCLK)
This 19.44, 38.88, 77.76 or 155.52 MHz nominally 50%
duty factor byte rate output clock (CMOS) is aligned to
RXPD0 to RXPD7 byte serial output data.
RXPD0 to RXPD7 and FP are updated on the falling edge
of RXPCLK.
Other operating modes
D
A transmitter-to-receiver loopback mode is available for
diagnostic purposes. When DLEN is LOW, the differential
serial data output from the transmitter is routed to the
serial-to-parallel block in place of the normal data stream
(RXSD), at the serial data rate.
L
The line loopback circuitry consists of alternate clock and
data output drivers. For the TZA3005, it selects the source
of the data and clock signals output on TXSD and
TXSCLK. When LLEN is HIGH, it selects data and clock
signals from the parallel-to-serial converter block. When
LLEN is LOW, it forces the output data multiplexer to select
data and clock signals from the RXSD and RXSCLK
1997 Aug 05
INE
IAGNOSTIC
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
L
OOPBACK
L
OOPBACK
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inputs, and a receive-to-transmit loopback can be
established at the serial data rate. Diagnostic loopback
and line loopback can be active at the same time.
Receiver framing
A typical reframe sequence involving byte realignment is
shown in Figure 3. Frame and byte boundary detection is
enabled on the rising edge on OOF and remains enabled
while OOF is HIGH. Boundaries are recognized on receipt
of the third A2 byte, the first data byte to be reported with
the correct byte alignment on the outgoing data bus
(RXPD0 to RXPD7). FP goes HIGH for one RXPCLK
cycle.
When interfacing with a section terminating device, OOF
must remain HIGH for a full frame after the initial frame
pulse. This is to allow the section terminating device to
verify internally that frame and byte alignment are correct
(see Fig.4). Since at least one framing pattern will have
been detected since the rising edge of OOF, boundary
detection will be disabled when OOF goes LOW.
The frame and byte boundary detection block is activated
by a rising edge on OOF, and remains active until an FP
pulse occurs AND OOF goes LOW (whichever occurs
last). Figure 4 shows a typical OOF timing pattern when
the TZA3005 is connected to a down stream section
terminating device. OOF remains HIGH for one full frame
after the first FP pulse. The frame and byte boundary
detection block is active until OOF goes LOW.
Figure 5 shows frame and byte boundary detection
activated on the rising edge of OOF, and deactivated by
the first FP pulse after OOF goes LOW.
Objective specification
TZA3005