ncp5214 ON Semiconductor, ncp5214 Datasheet - Page 17

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ncp5214

Manufacturer Part Number
ncp5214
Description
2-in-1 Notebook Ddr Power Controller
Manufacturer
ON Semiconductor
Datasheet

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Supply Voltage Undervoltage Monitor
VCCA pin and OCDDQ pin respectively. VCCAGD is set
HIGH if VCCA is higher than its preset threshold (derived
from VREF with hysteresis). The IC will enter S5 state if
VCCA fails while in S0 and both VDDQEN and VTTEN
remain HIGH.
Thermal Shutdown
entire IC is shutdown. The IC resumes normal operation
only after the junction temperature dropping below 125_C.
Power Good
comparator which continuously monitors the VDDQ
output voltage. The PGOOD is pulled low when the VDDQ
rises 12% above or drops 12% below the nominal
regulation point. The PGOOD becomes high impedance
when the VDDQ is within ±12% of the preset nominal
regulation voltage. A 100 kW resistor is recommended to
connect between PGOOD and VCCA as pull−up resistor
for logic level output.
Overvoltage Protection
of the nominal regulation output voltage, the controller
turns off the high−side MOSFET and turns on the low−side
The IC continuously monitors VCCA and VIN through
When the chip junction temperature exceeds 150_C, the
The PGOOD is an open−drain output of a window
When the VDDQ output is above 106% but below 130%
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NCP5214
17
MOSFET to discharge the excessive output voltage. When
the VDDQ output voltage goes back down to the nominal
regulation voltage, normal switching cycles are resumed.
When the VDDQ output exceeds 130% (typ) of the
nominal regulation voltage for 4 consecutive internal clock
cycles, the controller sets overvoltage fault, the device is
latched off by turning off both the high−side and low−side
MOSFETs. The overvoltage fault latch can be reset and the
controller can be restarted by toggling VDDQEN, VCCA,
or VIN.
Undervoltage Protection
lighter loads, when the VDDQ falls below 94% of the
nominal regulation voltage, the reduced switching
frequency is raised up back to the maximum switching
frequency. When VDDQ voltage is back to nominal
regulation voltage, the normal S3 power−saving operation
is resumed. In both S0 and S3 modes, when the VDDQ falls
below 65% (typ) of the nominal regulation voltage for 4
consecutive internal clock cycles, the undervoltage fault is
set, the device is latched off by turning off both the
high−side and low−side MOSFETs. The output is
discharged by the load current. The load current and output
capacitance determine the discharge rate. Cycling
VDDQEN, VCCA, or VIN can reset the undervoltage fault
latch and restart the controller.
In S3 power−saving mode with reduced switching at

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