lt3070 Linear Technology Corporation, lt3070 Datasheet - Page 16

• Manufacturer Part Number: lt3070
• Description: 5a, Low Noise, Programmable Output, 85mv Dropout Linear Regulator
• Manufacturer: Linear Technology Corporation

ApplicAtions inFormAtion
LT3070
component cost savings. The LT3070 steps to the next
level of performance for the latest generation FPGAs, DSPs
and microprocessors. The simple versatility and benefits
derived from these circuits exceed the power supply needs
of today’s high performance microprocessors.
Programming Output Voltage
Three tri-level input pins, V
value of output voltage. Table 1 illustrates the 3-bit digital
word to output voltage resulting from setting these pins
high, low or allowing them to float.
These pins may be tied high or low by either pin-strapping
them to V
float may either actually float or require logic that has
Hi-Z output capability. This allows output voltage to be
dynamically changed if necessary.
Output voltage is selectable from a minimum of 0.8V to
a maximum of 1.8V in increments of 50mV. The MSB,
V
V
Output voltage is limited to 1.8V maximum by an internal
override of V
Table 1: V
X = Don’t Care, 0 = Low, Z = Float, 1 = High
The input logic low threshold is less than 250mV refer-
enced to GND and the logic high threshold is greater than
V
as set by a window comparator defines the logic Hi-Z
state.

O2
O0
V
BIAS
0
0
0
0
0
0
0
0
0
Z
Z
O2
, sets the pedestal voltage, and the LSB’s, V
increment V
– 250mV. The range between these two thresholds
V
0
0
0
Z
Z
Z
1
1
1
0
0
O1
O2
BIAS
-V
V
O0
O1
0
Z
1
0
Z
1
0
Z
1
0
Z
O0
or driving them with digital ports. Pins that
Settings vs Output Voltage
(default to low) when V
OUT
V
OUT(NOM)
.
0.80V
0.85V
0.90V
0.95V
1.00V
1.05V
1.10V
1.15V
1.20V
1.25V
1.30V
O2
V
Z
Z
Z
Z
Z
Z
Z
1
1
1
, V
O2
O1
V
and V
X
X
X
0
Z
Z
Z
1
1
1
O1
O2
V
1
0
Z
1
0
Z
1
0
Z
1
O0
= high.
O0
, select the
V
OUT(NOM)
1.35V
1.40V
1.45V
1.50V
1.55V
1.60V
1.65V
1.70V
1.75V
1.80V
O1
and
REF/BYP—Voltage Reference
This pin is the buffered output of the internal bandgap
reference and has an output impedance of ≅19kΩ. The
design includes an internal compensation pole at f
A 10nF REF/BYP capacitor to GND creates a lowpass pole
at f
voltage noise to about 10µV
ence. The LT3070 only soft-starts the reference voltage
during an initial turn-on sequence. If the EN pin is toggled
low after initial turn-on, the reference remains powered-up.
Therefore, toggling the EN pin from low to high does not
soft-start the reference. Only by turning the BIAS supply
voltage on and off will the reference be soft-started. Output
voltage noise is the RMS sum of the reference voltage
noise in addition to the amplifier noise.
The REF/BYP pin must not be DC loaded by anything except
for applications that parallel other LT3070 regulators for
higher output currents. Consult the Applications Section
on Paralleling for further details.
Output Voltage Margining
Two tri-level input pins, MARGSEL (polarity) and MARGTOL
(scale), select the polarity and amount of output voltage
margining. Margining is programmable in increments of
±1%, ±3% and ±5%. Margining is internally implemented
as a scaling of the reference voltage.
Table 2 illustrates the 2-bit digital word to output voltage
margining resulting from setting these pins high, low or
allowing them to float.
These pins may be set high or low by either pin-strapping
them to V
float may either actually float or require logic that has
“Hi-Z” output capability. This allows output voltage to be
dynamically margined if necessary.
The MARGSEL pin determines both the polarity and the ac-
tive state of the margining function. The logic low t hreshold
is less than 250mV referenced to GND and enables negative
voltage margining. The logic high threshold is greater than
V
The voltage range between these two logic thresholds as
BIAS
LP
– 250mV and enables positive voltage margining.
= 840Hz. The 10nF capacitor decreases reference
BIAS
or driving them with digital ports. Pins that
RMS
and soft-starts the refer-
C
= 4kHz.
3070f