s-8233bcft-tb-g Seiko Instruments Inc., s-8233bcft-tb-g Datasheet - Page 14

• Manufacturer Part Number: s-8233bcft-tb-g
• Description: Battery Protection Ic For 3-serial-cell Pack
• Manufacturer: Seiko Instruments Inc.

14
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233B Series
Over discharge condition
Delay circuits
CTL terminal
If any one of the battery voltages falls below the over discharge detection voltage (V
under normal condition and it continues for the over discharge detection delay time (t
discharging FET turns off and discharging stops. This condition is called the over discharge condition.
When the discharging FET turns off, the VMP terminal voltage becomes equal to the V
IC's current consumption falls below the power-down current consumption (I
the power-down condition. The VMP and VSS terminals are shorted by the R
discharge and power-down conditions.
The over charge detection delay time (t
over current detection delay time 1 (t
The delay times are calculated by the following equations:
[If the CTL logic is “normal”]<S-8233BA, S-8233BC, S-8233BE>
If the CTL terminal is floated under normal condition, it is pulled up to the V
the charging and discharging FETs turn off to inhibit charging and discharging. Both charging and
discharging are also inhibited by applying the VCC terminal to the CTL terminal externally. At this time,
the VMP and VCC terminals are shorted by the R
[If the CTL logic is“reverse”]<S-8233BB, S-8233BD>
The power-down condition is canceled when the charger is connected and the voltage between VMP and
V
or higher than the over discharge release voltage (V
changes to the normal condition.
Caution The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The
When the CTL terminal becomes equal to V
back to their appropriate conditions for the battery voltages.
When the CTL terminal becomes equal to V
to inhibit charging and discharging. If the CTL terminal is floated under normal condition, charging and
discharging are enabled and go back to their appropriate conditions for the battery voltages.
Caution Please note unexpected behavior might occur when electrical potential difference
t
t
t
CU
DD
IOV1
SS
[S] =Delay factor ( 1.07, 2.13, 3.19)×C4 [uF]
[S] =Delay factor ( 0.20, 0.40, 0.60)×C5 [uF]
is 3.0 V or higher (over current detection voltage 3). When all the battery voltages becomes equal to
[S]=Delay factor ( 0.10, 0.20, 0.30)×C6 [uF]
delay time cannot be changed via an external capacitor.
between the CTL pin ('L' level) and VSS is generated through the external filter
(R
VSS
and C
Min.
VSS
) as a result of input voltage fluctuations.
Typ.
I0V1
Max.
Seiko Instruments Inc.
) are changed with external capacitors (C4 to C6).
CU1
to t
SS
SS
CU3
potential, both the charging and discharging FETs turn off
potential, charging and discharging are enabled and go
VCM
), over discharge detection delay time (t
resistor.
DU
) in this condition, the over discharge condition
CC
PDN
potential in the IC, and both
VSM
). This condition is called
resistor under the over
DD
) during discharging
SS
DD
DD1
voltage and the
) or longer, the
Rev.4.3
to t
DD3
), and
_00