ncp1651 ON Semiconductor, ncp1651 Datasheet - Page 22

• Manufacturer Part Number: ncp1651
• Description: Single Stage Power Factor Controller
• Manufacturer: ON Semiconductor

There is a hysteresis of 30 C on this circuit, which will allow
the chip to cool down to 130 C before resuming operation.
circuit will be operational and the V
10.8 and 9.8 volts.
sufficient to maintain operation, the drive of the chip will be
inhibited and the divide−by−eight timer will be invoked.
This will normally occur when the output is overloaded.
Under this condition, the divide−by−eight counter will count
for 8 V
will be enabled and the circuit will attempt to start. If the
failure has been corrected, the output will come up and the
circuit will resume normal operation. If not, another cycle
will begin. The waveforms for overload timeout are shown
in Figure 3.
can be used to inhibit the operation of the chip by reducing
the FB/SD pin voltage to less than 0.6 volts. When a
shutdown signal is issued, the output of the shutdown
comparator goes low. This immediately ceases the operation
of the unit by OR’ing that signal to the output of the PWM
logic, and holding the driver in its low state.
to the reset pin of the divide−by−eight counter. The counter
reset pin sets its count to seven. As long as the reset pin is
low, the counter will remain at seven. When the shutdown
signal is removed, the reset pin will go high, and the counter
will continue to count to eight. The counter is triggered on
the negative edge of the startup enable signal. This means
that a shutdown signal that is removed on the upward V
slope will be in the 7 count for the remaining rise and fall of
that V
the V
also insures that the unit will commence operation in less
than two V
operation is shown in Figure 3. The count for the
divide−by–eight counter is shown as 7, 7, 7, 8 which
illustrates the operation of the reset function.
reaches the lower UVLO limit (i.e. 9.8 volts), the unit will
resume operation on the following V
shutdown signal is terminated on the V
unit will resume operation on the second V
AC Reference Buffer
by the AC error amplifier to be converted into a current to
be summed with the ramp compensation signal and the
instantaneous current signal.
While in the overtemperature shutdown mode, the startup
Insufficient V
Shutdown The NCP1651 has a shutdown circuit that
The inverted output of the shutdown comparator is fed in
This system assures that the unit will not be enabled until
If the shutdown signal is terminated before the V
The AC reference buffer converts the voltage generated
CC
CC
CC
voltage has a full discharge cycle available, and it
cycle and will change to 8 on the next cycle.
cycles. At the end of the eighth cycle the driver
CC
cycles. A timing diagram of this mode of
CC
If the level of the V
CC
CC
down slope, and if the
CC
will cycle between
upward slope, the
CC
CC
down slope.
voltage is not
CC
voltage
http://onsemi.com
CC
NCP1651
22
current by creating a current equal to the voltage difference
between the AC error amplifier output and the 2.9 volt
reference dropped across the 6.7 kW resistor. The bipolar
transistor level shifts the voltage and maintains the proper
current into the current mirror. The current mirror has a
1:1 ratio and delivers its output current to the PWM input.
This current is summed with the currents of the ramp
compensation signal and the instantaneous current signal to
determine the turn−off point in the switching cycle.
Startup Circuit
providing the initial charge on the V
as a timer for the startup, overcurrent, and shutdown modes
of operation. Due to the nature of this circuit, this chip must
be biased using the startup circuit and an auxiliary winding
on the power transformer. Attempting to operate this chip
off of a fixed voltage supply will cause the chip to latch up
in some modes of operation.
current for startup power. On the application of input voltage,
the high voltage startup circuit is enabled and current is drawn
from the rectified AC line to charge the V
for the UVLO circuit (10.8 volts typical), the startup circuit
is disabled, and the PWM circuit is enabled. With the
NCP1651 enabled, the bias current increases from its
standby level to the operational level. The divide−by−eight
counter is preset to the count of 7, so that on startup the chip
will not be operational on the first cycle. The second V
cycle will be number 8, and the chip will be allowed to start
at this time. In the shutdown mode, the V
the 7 count state until the shutdown signal is removed. This
Comp
The buffer’s transfer function is:
The buffer amplifier, converts the input voltage to a
The startup circuit serves several functions. In addition to
A high voltage FET is biased as a current source to provide
When the voltage on the V
AC
3
Figure 37. AC Reference Buffer Schematic
ERROR
AMP
AC
i out + (2.9 V * V ac(ea) ) 6.7 k
2.9 V
Unity Gain Amplifier
+
−
+
−
CC
cap reaches the turn on point
CURRENT
MIRROR
i
1
6.7 k
CC
capacitor, it serves
CC
CC
cap.
cycle is held in
i
16 k
1
PWM,
Ramp
Comp
Current
Sense
Amp
CC