ncp1560hdr2g ON Semiconductor, ncp1560hdr2g Datasheet - Page 16

• Manufacturer Part Number: ncp1560hdr2g
• Description: Full Featured Voltage Mode Pwm Controller
• Manufacturer: ON Semiconductor

Maximum Duty Cycle
time of OUT1 by comparing the FF Ramp to V
FF Ramp voltage exceeds V
DC Comparator goes high. This will reset the Output Latch,
thus turning OFF the outputs and limiting the duty cycle.
desired DC if the operating frequency is known. The
maximum ON time is set by adjusting the FF Ramp to reach
V
The maximum ON time should be set for the minimum line
voltage. As line voltage increases, the slope of the FF Ramp
increases. This reduces the duty cycle below DC
is a desirable feature as the duty cycle is inversely
proportional to line voltage.
to set V
0.88 V. If the pin is floating, V
equivalent to 60% or 80% of a 1.5 V FF Ramp. V
be adjusted to other values by using an external resistor
network on the DC
line voltage is 36 V, R
300 kHz and a maximum duty cycle of 70% is required,
V
from the DC
limit can be disabled connecting a 100 kW resistor between
the DC
Oscillator Ramp
FF Ramp
DC(inv)
DC(inv)
A dedicated internal comparator limits the maximum ON
Duty cycle is defined as:
Therefore, the maximum ON time can be set to yield the
An internal resistor divider from a 2.0 V reference is used
This can be achieved by connecting a 45.3 kW resistor
0 V
0 V
V DC(inv) +
Figure 33. Maximum ON Time Limit Waveforms
MAX
DC(inv)
in a time equal to t
is calculated as follows:
V DC(inv) +
t
on(max)
and V
MAX
. If the DC
T
88.2 mA
REF
pin to GND. The maximum duty cycle
DC +
MAX
FF
10 pF
I FF
pins.
pin. For example, if the minimum
is 434 kW, operating frequency is
MAX
t on
T
6.7 kW
C FF
on(max)
DC(inv)
+ t on
6.7 kW
pin is grounded, V
125 kW
DC(inv)
, the output of the Max
as shown in Figure 33.
125 kW
2.33 ms
f
t on(max)
is 1.19 V. This is
+1.10 V
DC(inv)
MAX
DC(inv)
DC(inv)
V
, which
http://onsemi.com
. If the
2 V
DC(inv)
can
is
16
5.0 V Reference
The reference output is biased directly from V
supply up to 6 mA. Load regulation is 50 mV and line
regulation is 100 mV within the specified operating range.
0.1 mF ceramic capacitor. The reference output is disabled
when an UV fault is present.
PWM Comparator
the FF Ramp by means of the PWM Comparator. The
external error amplifier drives the V
0.7 V offset between the V
Comparator inverting input. The offset is provided by a
series diode and resistor. If the voltage on the V
below 0.7 V, the outputs are disabled.
OFF the outputs once the FF Ramp voltage exceeds the
offset V
DC from 0% to DC
where, V
threshold.
Soft−Start
steady state operation, thus reducing startup stress and
surges on the system. The duty cycle is limited during a
soft−start sequence by comparing the Oscillator Ramp to the
SS voltage (V
the SS pin once faults are removed and V
The Soft−Start Comparator controls the duty cycle while the
SS voltage is below 2.0 V. Once V
the Oscillator Ramp voltage and the Soft−Start Comparator
does not limit the duty cycle. Figure 34 shows the
relationship between the outputs duty cycle and the
soft−start voltage.
Oscillator
Ramp
OUT2
OUT1
The NCP1560 includes a precision 5.0 V reference output.
It is recommended to bypass the reference output with a
The output of an external error amplifier is compared to
The PWM Comparator controls the duty cycle by turning
Soft−start (SS) allows the converter to gradually reach
A 6.2 mA current source starts to charge the capacitor on
V EA(L) t V EA t
EA
Figure 34. Soft−Start Timing Diagram
EA(L)
voltage. The V
SS
) by means of the Soft−Start Comparator.
is the PWM comparator lower input
MAX
is given by the equation below:
EA
186.56 pf
I FF
range required to control the
EA
SS
DC
reaches 2.0 V, it exceeds
input and the PWM
EA
f
AUX
) V EA(L)
input. There is a
AUX
reaches 11 V.
EA
and it can
input is
V
SS