ncp1250 ON Semiconductor, ncp1250 Datasheet - Page 5

• Manufacturer Part Number: ncp1250
• Description: Ncp1250 Current-mode Pwm Controller For Off-line Power Supplies
• Manufacturer: ON Semiconductor

4. For design robustness, we recommend to inject 60 mA as a minimum at the lowest input line voltage.
5. Guaranteed by design
6. See characterization table for linearity over negative bias voltage
7. A 1 MW resistor is connected from pin 3 to the ground for the measurement.
ELECTRICAL CHARACTERISTICS
(For typical values T
CURRENT COMPARATOR
INTERNAL OSCILLATOR
FEEDBACK SECTION
FREQUENCY FOLDBACK
INTERNAL SLOPE COMPENSATION
PROTECTIONS
T
T
hysteresis
T
Symbol
V
latch−blank
latch−count
V
IOPPo
IOOPv
IOOPv
V
V
IOPPs
latch−del
V
R
Timer
f
F
V
T
D
fold,end
T
f
f
V
V
TSS
V
Skip
f
swing
I
freeze
R
R
freeze
Limit2
OSC
OSC
ratio
jitter
trans
ramp
ramp
DEL
latch
LEB
max
skip
fold
fold
up
eq
Maximum internal current setpoint – T
Default internal voltage set point for frequency foldback trip point – 45% of V
Internal peak current setpoint freeze ([31% of V
Propagation delay from current detection to gate off−state
Leading Edge Blanking Duration
Internal soft−start duration activated upon startup, auto−recovery
Setpoint decrease for pin 3 biased to –250 mV – (Note 6)
Voltage setpoint for pin 1 biased to −250 mV – (Note 6), T
Voltage setpoint for pin 1 biased to −250 mV – (Note 6), T
Setpoint decrease for pin 3 grounded
Oscillation frequency (65 kHz version)
Oscillation frequency (100 kHz version)
Maximum duty−cycle
Frequency jittering in percentage of f
Swing frequency
Internal pull−up resistor
Equivalent ac resistor from FB to GND
Pin 2 to current setpoint division ratio
Feedback voltage below which the peak current is frozen
Frequency folback level on the feedback pin – [45% of maximum peak current
Transition frequency below which skip−cycle occurs
End of frequency foldback feedback leve, F
Skip−cycle level voltage on the feedback pin
Hysteresis on the skip comparator – (Note 5)
Internal ramp level @ 25°C – (Note 7)
Internal ramp resistance to CS pin
Latching level input
Blanking time after drive turn off
Number of clock cycles before latch confirmation
OVP detection time constant
Internal auto−recovery fault timer duration
J
= 25°C, for min/max values T
OSC
J
Rating
J
= −40°C to +125°C, Max T
= −40°C to 125°C – pin 3 grounded
sw
http://onsemi.com
= F
limit
min
)
5
J
J
= 25°C
= −40°C to 125°C
J
= 150°C, V
limit
CC
= 12 V unless otherwise noted)
Pin
4
3
3
4
4
−
3
3
3
3
−
−
−
−
−
2
2
−
2
−
−
−
−
4
4
3
1
−
1
−
Min
0.72
0.51
0.50
100
2.7
61
92
76
22
31.3
0.55
0.55
1.05
Typ
357
250
100
300
100
240
350
300
600
0.8
4.0
4.2
1.5
2.5
3.0
1.0
4.0
65
80
±5
20
16
26
30
20
0
0.88
0.60
0.62
Max
150
108
3.3
71
84
30
Unit
kHz
kHz
kHz
mV
mV
mV
mV
mV
ms
kW
kW
kW
ms
Hz
ns
ns
ms
ns
%
%
%
%
V
V
V
V
V
V
V