tc58v64bft TOSHIBA Semiconductor CORPORATION, tc58v64bft Datasheet - Page 15

• Manufacturer Part Number: tc58v64bft
• Description: 64-mbit Bits Cmos Nand E2prom
• Manufacturer: TOSHIBA Semiconductor CORPORATION

PIN FUNCTIONS
are configured as shown in Figure 1.
The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs
Command Latch Enable: CLE
command into the internal command register. The command is latched
into the command register from the I/O port on the rising edge of the
Address Latch Enable: ALE
or input data into the internal address/data register.
High.
Chip Enable:
signal is ignored when device is in Busy state (
will not enter Standby mode even if the CE input goes High. The CE signal must stay Low during the Read
mode Busy state to ensure that memory array data is correctly transferred to the data register.
Write Enable:
Read Enable:
I/O Port: I/O1 to 8
device.
Write Protect:
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy:
Busy state (
(
WE signal while CLE is High.
RY
The CLE input signal is used to control loading of the operation mode
The ALE signal is used to control loading of either address information
Address information is latched on the rising edge of WE if ALE is
Input data is latched if ALE is Low.
The device goes into a low-power Standby mode when CE goes High during a Read operation. The CE
The WE signal is used to control the acquisition of data from the I/O port.
The RE signal controls serial data output. Data is available t
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
The
/
BY
RY
= H) after completion of the operation. The output buffer for this signal is an open drain.
/
BY
RY
RY
output signal is used to indicate the operating condition of the device. The
CE
/
RE
BY
WE
WP
/
BY
= L) during the Program, Erase and Read operations and will return to Ready state
RY
/
BY
= L), such as during a Program or Erase operation, and
REA
after the falling edge of RE .
CLE
ALE
I/O1
I/O2
I/O3
I/O4
WE
WP
V
V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SS
SS
Figure 1. Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
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TC58V64BFT
RY
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
/
BY
RE
RY
V
CE
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
V
CC
CC
signal is in
/
BY