m58wr032fb STMicroelectronics, m58wr032fb Datasheet
m58wr032fb
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m58wr032fb Summary of contents
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... November 2004 32 Mbit (2Mb x16, Multiple Bank, Burst) 1.8V Supply Flash Memory Figure 1. Package ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Codes: M58WR032FT (Top): 8814h M58WR032FB (Bottom): 8815h PACKAGE – Compliant with Lead-Free Soldering Processes – Lead-Free Versions M58WR032FT M58WR032FB FBGA VFBGA56 (ZB) 7 ...
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... M58WR032FT, M58WR032FB TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. VFBGA Connections (Top view through package Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Inputs (A0-A20 Data Input/Output (DQ0-DQ15 Chip Enable (E Output Enable (G Write Enable (W) ...
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... Program Status Bit (SR4 Status Bit (SR3 Program Suspend Status Bit (SR2 Block Protection Status Bit (SR1 Bank Write/Multiple Word Program Status Bit (SR0 Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read Select Bit (CR15 X-Latency Bits (CR13-CR11 Wait Polarity Bit (CR10 M58WR032FT, M58WR032FB 3/86 ...
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... M58WR032FT, M58WR032FB Data Output Configuration Bit (CR9 Wait Configuration Bit (CR8 Burst Type Bit (CR7 Valid Clock Edge Bit (CR6 Wrap Burst Bit (CR3 Burst length Bits (CR2-CR0 Table 9. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 10. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 6. X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 7 ...
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... Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 27. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 28. Top Boot Block Addresses, M58WR032FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 29. Bottom Boot Block Addresses, M58WR032FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 APPENDIX B.COMMON FLASH INTERFACE Table 30. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 31. CFI Query Identification String Table 32. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 33 ...
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... M58WR032FT, M58WR032FB Figure 28.Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 29.Protection Register Program Flowchart and Pseudo Code Figure 30.Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 31.Quadruple Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Quadruple Enhanced Factory Program Pseudo Code APPENDIX D.COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 40 ...
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... Figure 4. eter Blocks are located at the top of the memory address space for the M58WR032FT and at the bottom for the M58WR032FB. Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed ...
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... M58WR032FT, M58WR032FB Figure 2. Logic Diagram DDQ A0-A20 W E M58WR032FT G M58WR032FB SSQ 8/86 Table 1. Signal Names A0-A20 DQ0-DQ15 DQ0-DQ15 WAIT K L WAIT DDQ AI09300 V SSQ NC Address Inputs Data Input/Outputs, Command Inputs Chip Enable ...
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... W WAIT A16 DQ12 DQ6 DQ4 DQ2 DQ13 DQ11 DQ10 DQ5 V DD DQ3 Bank Size Parameter Blocks 4 Mbits 8 blocks of 4 KWords 4 Mbits 4 Mbits 4 Mbits 4 Mbits 4 Mbits M58WR032FT, M58WR032FB A18 A6 A4 A17 A5 A3 A19 DQ1 E A0 DQ9 DQ0 G V DDQ ...
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... KWord 1BFFFFh 1C0000h 32 KWord 1C7FFFh 1F0000h 32 KWord Parameter 1F7FFFh Bank 1F8000h 4 KWord 1F8FFFh 1FF000h 4 KWord 1FFFFFh 10/86 M58WR032FB - Bottom Boot Block Address lines A20-A0 000000h 000FFFh 8 Main Blocks 007000h Parameter 007FFFh Bank 008000h 00FFFFh 038000h 03FFFFh 040000h 047FFFh 8 Main Blocks Bank 1 ...
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... V RPH Note: Each device in a system should have Voltages DDQ ramic capacitor close to the pin (high frequen- cy, inherently low inductance capacitors M58WR032FT, M58WR032FB or Reset provides the power DD provides the power DDQ . V DD DDQ or can use a separate supply. ...
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... M58WR032FT, M58WR032FB should be as close as possible to the pack- age). See Figure 9., AC Measurement Load Cir- cuit. The PCB track widths should be sufficient BUS OPERATIONS There are six standard bus operations that control the device. These are Bus Read, Bus Write, Ad- dress Latch, Output Disable, Standby and Reset ...
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... Bank Erase Setup 90h Read Electronic Signature 98h Read CFI Query B0h Program/Erase Suspend C0h Protection Register Program Program/Erase Resume, Block Erase Confirm, Bank Erase Confirm, Block D0h Unlock Confirm or Enhanced Factory Program Confirm FFh Read Array M58WR032FT, M58WR032FB Command 13/86 ...
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... M58WR032FT, M58WR032FB COMMAND INTERFACE - STANDARD COMMANDS The following commands are the basic commands used to read, write to and configure the device. Refer to Table 5., Standard Commands, in con- junction with the following text descriptions. Read Array Command The Read Array command returns the addressed bank to Read Array mode ...
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... If a Program command is issued during a Block Erase Suspend, then the erase cannot be re- sumed until the programming operation has com- pleted possible to accumulate suspend operations. For example: suspend an erase oper- M58WR032FT, M58WR032FB DUAL OPERATIONS AND section for C., Figure 25., Program Suspend ...
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... M58WR032FT, M58WR032FB ation, start a programming operation, suspend the programming operation then read the array. See APPENDIX C., Figure 25., Program Suspend & Resume Flowchart and Pseudo 27., Erase Suspend & Resume Flowchart and Pseudo Code, for flowcharts for using the Pro- gram/Erase Resume command. ...
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... Write X 2 Write PRA 2 Write CRD (3) 2 Write BKA or BA (3) 2 Write BKA or BA (3) 2 Write BKA or BA M58WR032FT, M58WR032FB BLOCK LOCKING, for a detailed ex- APPENDIX C., Figure 28., Locking Bus Operations 2nd Cycle Data Op. Add FFh WA Read (2) 70h Read BKA (2) 90h Read BKA ...
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... M58WR032FT, M58WR032FB Table 6. Electronic Signature Codes Manufacturer Code Top (M58WR032FT) Device Code Bottom(M58WR032FB) Locked Unlocked Block Protection Locked and Locked-Down Unlocked and Locked-Down Reserved Configuration Register ST Factory Default Protection Register Lock OTP Area Permanently Locked Protection Register Note Configuration Register. Figure 5. Protection Register Memory Map ...
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... Program Command. The second bus cycle latches the Address and the Data of the first word to be written. The third bus cycle latches the Address and the Data of the second word to be written. M58WR032FT, M58WR032FB Table 14., Pro- Cycles. Table 14., Pro- Cycles data IL C ...
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... M58WR032FT, M58WR032FB The fourth bus cycle latches the Address and the Data of the third word to be written. The fifth bus cycle latches the Address and the Data of the fourth word to be written and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the pro- gramming has started ...
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... See the section on the tails. If the Program and Verify Phase has successfully completed the memory returns to Read mode. If the P/E.C. fails to program and reprogram a given location, the error will be signaled in the Status Register. M58WR032FT, M58WR032FB STATUS REGISTER for more de- 21/86 ...
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... M58WR032FT, M58WR032FB Table 7. Factory Program Commands Command Phase 2 Bank Erase (4) 3 Double Word Program Quadruple Word 5 (5) Program Setup, 2+ Enhanced Program n+1 Factory (6) Program Verify, Exit n+1 Setup, 5 first Load First Program & Verify Quadruple Enhanced Subsequent Factory 4 Loads Program (5,6) Subsequent Program & ...
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... Erase Suspend Status Bit (SR6). The Suspend Status bit indicates that an Erase opera- tion has been suspended or is going to be sus- M58WR032FT, M58WR032FB pended in the addressed block. When the Erase Suspend Status bit is High (set to ‘1’), a Program/ Erase Suspend command has been issued and ...
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... M58WR032FT, M58WR032FB or Erase operation. Indeterminate results can oc- cur if V becomes invalid during an operation. PP When the V Status bit is Low (set to ‘0’), the volt- PP age on the V pin was sampled at a valid voltage; PP when the V Status bit is High (set to ‘1’), the V PP ...
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... SR7 = ‘0’ Program or erase operation in addressed bank SR7 = ‘1’ Not Allowed '1' SR7 = ‘0’ the device is NOT ready for the next word Status SR7 = ‘1’ the device is exiting from EFP '0' SR7 = ‘0’ M58WR032FT, M58WR032FB Definition the device is ready for the next Word 25/86 ...
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... M58WR032FT, M58WR032FB CONFIGURATION REGISTER The Configuration Register is used to configure the type of bus access that the memory will per- form. Refer to READ MODES on read operations. The Configuration Register is set through the Command Interface. After a Reset or Power-Up the device is configured for asynchronous page read (CR15 = 1) ...
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... WAIT is active one data cycle before wait state (default) 0 Interleaved 1 Sequential (default) 0 Falling Clock edge 1 Rising Clock edge (default) 0 Wrap 1 No Wrap (default) 001 4 Words 010 8 Words 011 16 Words 111 Continuous (CR7 must be set to ‘1’) (default) M58WR032FT, M58WR032FB Table 10., Burst Type Definition. Description 27/86 ...
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... M58WR032FT, M58WR032FB Table 10. Burst Type Definition 4 Words Start Inter- Add Sequen-tial Sequential leaved 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 ... 7 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 ... 28/86 8 Words 16 Words Interleaved Sequential 0-1-2-3-4-5- 0-1-2-3-4-5-6-7-8-9- 6-7 10-11-12-13-14-15 1-2-3-4-5-6-7-8-9- 1-0-3-2-5-4- 10-11-12-13-14-15- 7-6 0 2-3-0-1-6-7- 2-3-4-5-6-7-8-9-10- 4-5 11-12-13-14-15-0-1 3-2-1-0-7-6- 3-4-5-6-7-8-9-10-11- 5-4 12-13-14-15-0-1-2 7-6-5-4-3-2- 7-8-9-10-11-12-13- 1-0 14-15-0-1-2-3-4-5-6 Continuous Burst Interleaved 0-1-2-3-4-5-6-7- 8-9-10-11-12- 0-1-2-3-4-5-6... 13-14-15 1-0-3-2-5-4-7-6- 1-2-3-4-5-6-7- 9-8-11-10-13- ...15-WAIT-16-17- 12-15-14 18... 2-3-0-1-6-7-4-5- 2-3-4-5-6-7...15- 10-11-8-9-14- WAIT-WAIT-16- 15-12-13 17-18... 3-2-1-0-7-6-5-4- 3-4-5-6-7...15- 11-10-9-8-15- WAIT-WAIT- 14-13-12 WAIT-16-17-18... 7-8-9-10-11-12- 7-6-5-4-3-2-1-0- 13-14-15-WAIT- 15-14-13-12-11- WAIT-WAIT-16- 10-9-8 17... 12-13-14-15-16- 17-18... 13-14-15-WAIT- 16-17-18... 14-15-WAIT- WAIT-16-17-18.... 15-WAIT-WAIT- WAIT-16-17-18... ...
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... WAIT-16-17- WAIT-16 18-19-20 14-15- 14-15-WAIT- 14 WAIT- WAIT-16-17- WAIT-16-17 18-19-20-21 15-WAIT- 15-WAIT-WAIT- WAIT- 15 WAIT-16-17- WAIT-16- 18-19-20-21-22 17-18 8 Words Interleaved Sequential 0-1-2-3-4-5-6-7-8-9- 10-11-12-13-14-15 1-2-3-4-5-6-7-8-9- 10-11-12-13-14-15- WAIT-16 2-3-4-5-6-7-8-9-10- 11-12-13-14-15- WAIT-WAIT-16-17 3-4-5-6-7-8-9-10-11- 12-13-14-15-WAIT- 10 WAIT-WAIT- 16-17-18 7-8-9-10-11-12-13- 14-15-WAIT-WAIT- WAIT-16-17-18-19- 20-21-22 12-13-14-15-16-17- 18-19-20-21-22-23- 24-25-26-27 13-14-15-WAIT-16- 17-18-19-20-21-22- 23-24-25-26-27-28 14-15-WAIT-WAIT- 16-17-18-19-20-21- 22-23-24-25-26-27- 28-29 15-WAIT-WAIT- WAIT-16-17-18-19- 20-21-22-23-24-25- 26-27-28-29-30 M58WR032FT, M58WR032FB 16 Words Continuous Burst Interleaved Same as for Wrap (Wrap /No Wrap has no effect on Continuous Burst) 29/86 ...
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... M58WR032FT, M58WR032FB Figure 6. X-Latency and Data Output Configuration Example 1st cycle A20-A0 VALID ADDRESS tDELAY tAVK_CPU DQ15-DQ0 Note. Settings shown: X-latency = 4, Data Output held for one clock cycle Figure 7. Wait Configuration Example A20-A0 VALID ADDRESS DQ15-DQ0 WAIT CR8 = '0' CR10 = '0' ...
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... Word Page, Figure 11., the Wait state will not occur. Waveforms, for de- The WAIT signal can be configured to be active Low or active High (default) by setting CR10 in the Configuration Register. The WAIT signal is mean- ingful only in Synchronous Burst Read mode, in M58WR032FT, M58WR032FB 31/86 ...
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... M58WR032FT, M58WR032FB other modes, WAIT is always asserted (except for Read Array mode). See Table 21., Synchronous Read AC Character- istics, and Figure 12., Synchronous Burst Read AC Waveforms, for details. Synchronous Burst Read Suspend. A chronous Burst Read operation can be suspend- ed, freeing the data bus for other higher priority devices ...
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... CFI Query Register Signature Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes M58WR032FT, M58WR032FB 11 and 12 show the dual operations possi- Program/ Block Program Erase Erase Suspend Yes Yes Yes – – Yes – – ...
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... M58WR032FT, M58WR032FB BLOCK LOCKING The M58WR032FT/B features an instant, individu- al block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. Lock/Unlock - this first level allows software- only control of block locking. Lock-Down - this second level requires hardware interaction before locking can be changed ...
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... All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status transition locked block will restore the previous DQ0 value, giving a 111 or 110. IH Next Protection Status (WP, DQ1, DQ0) After After Block Lock Block Unlock Command Command 1,0,1 1,0,0 1,0,1 1,0,0 1,1,1 1,1,0 1,1,1 1,1,0 0,0,1 0,0,0 0,0,1 0,0,0 0,1,1 0,1,1 and M58WR032FT, M58WR032FB (1) After Block After Lock-Down WP transition Command 1,1,1 0,0,0 1,1,1 0,0,1 1,1,1 0,1,1 1,1,1 0,1,1 0,1,1 1,0,0 0,1,1 1,0,1 0,1,1 1,1,1 or 1,1,0 35/86 (3) ...
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... M58WR032FT, M58WR032FB PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES The Program and Erase times and the number of Program/ Erase cycles per block are shown in ble 14. Exact erase times may change depending on the memory array condition. The best case is when all the bits in the block or bank are at ‘0’ (pre- programmed). The worst case is when all the bits in the block or bank are at ‘ ...
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... Quadruple Word Word Quad-Enhanced Factory Enhanced Factory (4) Quadruple Word Word Quad-Enhanced (4) Factory (4) Quadruple Word = 1.7V to 2.24V. DDQ = 25°C ±5°C for Quadruple Word, Double Word and Quadruple Enhanced Factory Program. A M58WR032FT, M58WR032FB Typical after Typ 100k W/E Max Unit Cycles 0.25 2.5 0.8 4 3.5 8 100 µ ...
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... M58WR032FT, M58WR032FB MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- Table 15 ...
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... Input Capacitance IN C Output Capacitance OUT Note: Sampled only, not 100% tested. M58WR032FT, M58WR032FB Conditions summarized in and AC Measurement should check that the operating conditions in their circuit match the operating conditions when rely- ing on the quoted parameters. M58WR032FT, M58WR032FB 60 70 Min Max Min 1.7 2 1.7 1.7 2.24 1.7 11 ...
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... M58WR032FT, M58WR032FB Table 18. DC Characteristics - Currents Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO Supply Current Asynchronous Read (f=6MHz) Supply Current Synchronous Read (f=54MHz) I DD1 Supply Current Synchronous Read (f=66MHz) I Supply Current (Reset) DD2 I Supply Current (Standby) DD3 I Supply Current (Automatic Standby) ...
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... Program Voltage-Logic PP1 Program Voltage Factory PPH PP V Program or Erase Lockout PPLK V V Lock Voltage LKO pin Extended High Voltage RPH M58WR032FT, M58WR032FB Test Condition Min –0.5 V –0.4 DDQ I = 100µ –100µA V –0.1 OH DDQ Program, Erase 1.1 Program, Erase 11 ...
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... M58WR032FT, M58WR032FB Figure 10. Asynchronous Random Access Read AC Waveforms 42/86 ...
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... Figure 11. Asynchronous Page Read AC Waveforms M58WR032FT, M58WR032FB 43/86 ...
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... M58WR032FT, M58WR032FB Table 20. Asynchronous Read AC Characteristics Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid (Random) AVQV ACC t t Address Valid to Output Valid (Page) AVQV1 PAGE (1) t Address Transition to Output Transition t OH AXQX t Chip Enable Low to Wait Valid ...
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... Figure 12. Synchronous Burst Read AC Waveforms M58WR032FT, M58WR032FB 45/86 ...
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... M58WR032FT, M58WR032FB Figure 13. Single Synchronous Read AC Waveforms 46/86 ...
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... Figure 14. Synchronous Burst Read Suspend AC Waveforms M58WR032FT, M58WR032FB 47/86 ...
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... M58WR032FT, M58WR032FB Figure 15. Clock input AC Waveform tKHKL Table 21. Synchronous Read AC Characteristics Symbol Alt t t AVKH AVCLKH t t ELKH ELCLKH t ELTV t EHEL t EHTZ t t KHAX CLKHAX t KHQV t CLKHQV t KHTV t KHQX t CLKHQX t KHTX t t LLKH ADVLCLKH t t KHKH CLK t KHKL t KLKH Note: 1. Sampled only, not 100% tested. ...
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... Figure 16. Write AC Waveforms, Write Enable Controlled M58WR032FT, M58WR032FB 49/86 ...
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... M58WR032FT, M58WR032FB Table 22. Write AC Characteristics, Write Enable Controlled Symbol Alt t t Address Valid to Next Address Valid AVAV WC t Address Valid to Latch Enable High AVLH (3) Address Valid to Write Enable High t AVWH t t Data Valid to Write Enable High DVWH DS t Chip Enable Low to Latch Enable High ...
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... Figure 17. Write AC Waveforms, Chip Enable Controlled M58WR032FT, M58WR032FB 51/86 ...
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... M58WR032FT, M58WR032FB Table 23. Write AC Characteristics, Chip Enable Controlled Symbol Alt t t Address Valid to Next Address Valid AVAV WC t Address Valid to Chip Enable High AVEH t Address Valid to Latch Enable High AVLH t t Data Valid to Chip Enable High DVEH Chip Enable High to Address Transition ...
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... Sampled only, not 100% tested important to assert RP in order to allow proper CPU initialization during Power-Up or Reset. tPHWL tPHEL tPHGL tPHLL Power-Up Test Condition During Program During Erase Other Conditions < 50ns. PLPH M58WR032FT, M58WR032FB tPLWL tPLEL tPLGL tPLLL tPLPH Reset AI06976 Unit Min ...
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... M58WR032FT, M58WR032FB PACKAGE MECHANICAL Figure 19. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline BALL "A1" Note: Drawing is not to scale. Table 25. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Package Mechanical Data millimeters Symbol Typ 0.660 b 0 ...
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... Figure 20. VFBGA56 Daisy Chain - Package Connections (Top view through package M58WR032FT, M58WR032FB AI07731b 55/86 ...
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... M58WR032FT, M58WR032FB Figure 21. VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package START POINT 56/ END POINT AI07755 ...
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... F = Lead-Free and RoHS Package, Tape & Reel Packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op- tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. M58WR032FT, M58WR032FB M58WR032FT ...
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... M58WR032FT, M58WR032FB APPENDIX A. BLOCK ADDRESS TABLES Table 28. Top Boot Block Addresses, M58WR032FT Size Bank # Address Range (KWord 1FF000-1FFFFF 1 4 1FE000-1FEFFF 2 4 1FD000-1FDFFF 3 4 1FC000-1FCFFF 4 4 1FB000-1FBFFF 5 4 1FA000-1FAFFF 6 4 1F9000-1F9FFF 7 4 1F8000-1F8FFF 8 32 1F0000-1F7FFF 9 32 1E8000-1EFFFF 10 32 1E0000-1E7FFF 11 32 1D8000-1DFFFF ...
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... M58WR032FT, M58WR032FB 30 32 0B8000-0BFFFF 29 32 0B0000-0B7FFF 28 32 0A8000-0AFFFF 27 32 0A0000-0A7FFF 26 32 098000-09FFFF 25 32 090000-097FFF 24 32 088000-08FFFF 23 32 080000-087FFF 22 32 078000-07FFFF 21 32 ...
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... M58WR032FT, M58WR032FB APPENDIX B. COMMON FLASH INTERFACE The Common Flash Interface is a JEDEC ap- proved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory ...
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... Address for Primary Algorithm extended Query table (see Table 34.) Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported Address for Alternate Algorithm extended Query table M58WR032FT, M58WR032FB Value ST Top (M58WR032FT) Bottom (M58WR032FB) "Q" "R" "Y" 39h NA NA 61/86 ...
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... M58WR032FT, M58WR032FB Table 32. CFI Query System Interface Information Offset Data V Logic Supply Minimum Program/Erase or Write voltage DD 1Bh 0017h bit BCD value in volts bit BCD value in 100 millivolts V Logic Supply Maximum Program/Erase or Write voltage DD 1Ch 0020h bit BCD value in volts ...
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... Number of identical-size erase block = 003Eh+1 33h 0000h Region 2 Information 34h 0001h Block size in Region 2 = 0100h * 256 byte 35h reserved Reserved for future erase block region information 38h M58WR032FT, M58WR032FB Description n in number of bytes Value 4 MByte x16 Async KByte ...
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... M58WR032FT, M58WR032FB Table 34. Primary Algorithm-Specific Extended Query Table Offset Data (P)h = 39h 0050h 0052h Primary Algorithm extended Query table unique ASCII string “PRI” 0049h (P+3)h = 3Ch 0031h Major version number, ASCII (P+4)h = 3Dh 0033h Minor version number, ASCII (P+5)h = 3Eh 00E6h Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte ...
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... See offset 28h for word width to determine the burst data output width. Data 02h Number of Bank Regions within the device Table 28. and Table 29. M58WR032FT, M58WR032FB Value 1 0080h 8 Bytes 16 Bytes Value 8 Bytes 4 4 ...
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... M58WR032FT, M58WR032FB Table 38. Bank and Erase Block Region 1 Information M58WR032FT (top) M58WR032FB(bottom) Offset Data Offset (P+1A)h = 53h 07h (P+1A)h = 53h (P+1B)h = 54h 00h (P+1B)h = 54h (P+1C)h = 55h 11h (P+1C)h = 55h (P+1D)h = 56h 00h (P+1D)h = 56h (P+1E)h = 57h 00h (P+1E)h = 57h (P+1F)h = 58h 01h (P+1F)h = 58h (P+20)h = 59h 07h (P+20)h = 59h (P+21)h = 5Ah 00h (P+21)h = 5Ah (P+22)h = 5Bh 00h ...
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... M58WR032FT, M58WR032FB Description Data Bank Regions 1 (Erase Block Type 2): BIts per cell, internal ECC 01h Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved Bank Region 1 (Erase Block Type 2): Page mode and ...
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... M58WR032FT, M58WR032FB M58WR032FT (top) M58WR032FB (bottom) Offset Data Offset (P+35)h = 6Eh 03h (P+3D)h = 76h (P+36)h = 6Fh 07h (P+37)h = 70h 00h (P+38)h = 71h 20h (P+39)h = 72h 00h (P+3A)h = 73h 64h (P+3B)h = 74h 00h (P+3C)h = 75h 01h (P+3D)h = 76h 03h (P+3E)h = 77h (P+3E)h = 77h (P+3F)h = 78h (P+3F)h = 78h Note: 1. The variable pointer which is defined at CFI offset 15h. ...
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... PP invalid error */ Error (1, 2) error_handler ( ) ; Program if (status_register.SR4==1) /*program error */ Error (1, 2) error_handler ( ) ; if (status_register.SR1==1) /*program to protect block error */ Block Error (1, 2) error_handler ( ) ; } Invalid) and SR4 (Program Error) can be made after each program operation or PP M58WR032FT, M58WR032FB /*see note (3)*/ "see note (3)"; AI06170b 69/86 ...
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... M58WR032FT, M58WR032FB Figure 23. Double Word Program Flowchart and Pseudo code Start Write 35h Write Address 1 & Data 1 (3, 4) Write Address 2 & Data 2 (3) Read Status Register (4) NO SR7 = 1 YES NO SR3 = 0 YES NO SR4 = 0 YES NO Program to Protected SR1 = 0 Block Error (1, 2) YES End Note: 1 ...
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... Program error_handler ( ) ; Error ( (status_register.SR==1) /*program to protect block error */ error_handler ( ) ; } Invalid) and SR4 (Program Error) can be made after each program operation or PP M58WR032FT, M58WR032FB addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) /*see note (4) */ /*see note (3) */ /*see note (3) */ /*see note (3) */ /*see note (3) */ /" ...
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... M58WR032FT, M58WR032FB Figure 25. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO SR2 = 1 YES Write FFh Read data from another address Write D0h (1) Write 70h Program Continues with Bank in Read Status Register Mode Note: The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command ...
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... V PP Invalid if (status_register.SR3==1) /*V PP invalid error */ Error (1) error_handler ( ) ; if ( (status_register.SR4==1) && (status_register.SR5==1) ) Command /* command sequence error */ Sequence Error (1) error_handler ( ) ; if ( (status_register.SR5== erase error */ Erase Error (1) error_handler ( ) ; Erase to Protected if (status_register.SR1==1) /*program to protect block error */ Block Error (1) error_handler ( ) ; } M58WR032FT, M58WR032FB /*see note ( see note (2) */ AI06174b 73/86 ...
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... M58WR032FT, M58WR032FB Figure 27. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register NO SR7 = 1 YES NO SR6 = 1 YES Write FFh Read data from another block or Program/Protection Register Program or Block Lock/Unlock/Lock-Down Write D0h (1) Write 70h Erase Continues with ...
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... NO error_handler () ; /*Check the locking state (see Read Block Signature table )*/ writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/ } M58WR032FT, M58WR032FB /* see note (1) */ /*see note (1) */ /*see note (1) */ AI06176b 75/86 ...
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... M58WR032FT, M58WR032FB Figure 29. Protection Register Program Flowchart and Pseudo Code Start Write C0h (3) Write Address & Data Read Status Register (3) NO SR7 = 1 YES NO SR3 = 0 YES NO SR4 = 0 YES NO Program to Protected SR1 = 0 Block Error (1, 2) YES End Note: 1. Status check of SR1 (Protected Block), SR3 (V after a sequence ...
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... SR0 = 0? YES Write PD2 ( 1) Read Status Register NO SR0 = 0? YES Write PDn ( 1) Read Status Register NO SR0 = 0? YES Write FFFFh / = M58WR032FT, M58WR032FB VERIFY PHASE Write PD1 ( 1) Address WA1 Read Status Register NO SR0 = 0? YES Write PD2 ( 1) Address WA2 Read Status Register NO SR0 = 0? YES Write PDn ...
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... M58WR032FT, M58WR032FB Enhanced Factory Program Pseudo Code efp_command(addressFlow,dataFlow, the number of data to be programmed */ { /* setup phase */ writeToFlash(addressFlow[0],0x30); writeToFlash(addressFlow[0],0xD0); status_register=readFlash(any_address); if (status_register.SR7==1){ /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ if (status_register.SR3==1) /*VPP invalid error*/ if (status_register.SR1==1) /*program to protect block error*/ } else{ /*Program Phase*/ do{ } while (status_register ...
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... Note: 1. Address can remain Starting Address WA1 (in which case the next Page is programmed) or can be any address in the same block. 2. The address is only checked for the first Word of each Page as the order to program the Words is fixed, so subsequent Words in each Page can be written to any address. M58WR032FT, M58WR032FB LOAD PHASE Write PD1 ...
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... M58WR032FT, M58WR032FB Quadruple Enhanced Factory Program Pseudo Code quad_efp_command(addressFlow,dataFlow, the number of pages to be programmed.*/ { /* Setup phase */ writeToFlash(addressFlow[0],0x75); for (i=0; i++; i< n){ /*Data Load Phase*/ /*First Data*/ writeToFlash(addressFlow[i],dataFlow[i,0]); /*at the first data of the first page, Quad-EFP may be aborted*/ if (First_Page) { status_register=readFlash(any_address); if (status_register.SR7==1){ ...
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... Ready (error) Erase Busy Erase Suspended Program Busy in Erase Suspend Program Busy in Erase Suspend Erase Suspend (Lock Error) Ready (error) EFP Busy EFP Verify Quad EFP Busy Quad EFP Busy M58WR032FT, M58WR032FB Erase Confirm P/E Clear Resume, Program/ Read status Block Erase ...
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... M58WR032FT, M58WR032FB Table 41. Command Interface States - Modify Table, Next Output WP Read Current CI State setup (2) Array (3,4) (FFh) (10/40h) Program Setup Erase Setup OTP Setup Program in Erase Suspend EFP Setup EFP Busy EFP Verify Quad EFP Setup Quad EFP Busy Lock/CR Setup Lock/CR Setup ...
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... Program Busy in Erase Suspend Program Busy in Erase Suspend Program Suspend in Erase Suspend Erase Suspend Ready (error) (2) EFP Busy (2) EFP Verify Quad EFP Busy (2) Quad EFP Busy M58WR032FT, M58WR032FB EFP Exit, Set CR Illegal Quad EFP Confirm Command (3) (03h) Exit (5) Ready Ready (Lock error) ...
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... M58WR032FT, M58WR032FB Table 43. Command Interface States - Lock Table, Next Output Lock/CR OTP Setup Current CI State (3) Setup (60h) Program Setup Erase Setup OTP Setup Program in Erase Suspend EFP Setup EFP Busy EFP Verify Quad EFP Setup Quad EFP Busy Lock/CR Setup Lock/CR Setup in ...
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... Program/Erase in one Bank, Synchronous read in another Bank Table 18., DC Characteristics - Definition. Small text changes. and t removed from Table 22., Write AC Characteristics, Write Enable AVEH and Table 23., Write AC Characteristics, Chip Enable M58WR032FT, M58WR032FB Currents. and Figure modified, notes added. Table 33., Device Controlled. 85/86 ...
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... M58WR032FT, M58WR032FB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...