stk14ee16 Simtek Corporation, stk14ee16 Datasheet - Page 14

• Manufacturer Part Number: stk14ee16
• Description: 512kx16 Autostore Nvsram
• Manufacturer: Simtek Corporation

Document Control #ML0069 Rev 1.0
STK14EE16
tile information is transferred into the SRAM cells.
After the t
again be ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the
nonvolatile storage elements.Care must be taken so
the controlling falling edge is glitch and ring free so
as not to double clock the read address.
DATA PROTECTION
The STK14EE16 protects data from corruption dur-
ing low-voltage conditions by inhibiting all externally
initiated STORE and WRITE operations. The low-
voltage condition is detected when V
If the STK14EE16 is in a WRITE mode (both E and
W low) at power-up, after a RECALL, or after a
STORE, the WRITE will be inhibited until a negative
transition on E or W is detected. This protects
against inadvertent writes during power up or brown
out conditions.
NOISE CONSIDERATIONS
The STK14EE16 is a high-speed memory and so
must have a high-frequency bypass capacitor of 0.1
µF connected between both V
ground plane with no plane break to chip V
leads and traces that are as short as possible. As
with all high-speed CMOS ICs, careful routing of
power, ground, and signals will reduce circuit noise.
BEST PRACTICES
nvSRAM products have been used effectively for
over 15 years. While ease-of-use is one of the prod-
uct’s main system values, experience gained work-
ing with hundreds of applications has resulted in the
following suggestions as best practices:
• The non-volatile cells in this nvSRAM product are
delivered from Simtek with 0x00 written in all
cells. Incoming inspection routines at customer or
contract manufacturer’s sites will sometimes
reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A8,
or 5A. End product’s firmware should not assume
an NV array is in a set programmed state. Rou-
tines that check memory content values to deter-
mine first time system configuration, cold or warm
boot status, etc. should always program a unique
NV pattern (i.e., repeating 4-byte pattern of 46 E6
49 53 hex) as part of the final system manufactur-
March, 2008
RECALL
cycle time, the SRAM will once
CC
CC
pins and V
<V
Simtek Confidential
SWITCH
SS
. Use
.
SS
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• Power up boot firmware routines should rewrite
• The autostore enabled/disabled feature will reset
• The V
LOW AVERAGE ACTIVE POWER
CMOS technology provides the STK14EE16 with
the benefit of power supply current that scales with
cycle time. Less current will be drawn as the mem-
ory cycle time becomes longer than 50 ns. Figure 4
shows the relationship between I
WRITE cycle time. Worst-case current consumption
is shown for commercial temperature range,
V
Only standby current is drawn when the chip is dis-
abled. The overall average current drawn by the
STK14EE16 depends on the following items:
CC
ing test to ensure these system routines work
consistently.
the nvSRAM into the desired state (autostore
enabled, etc.). While the nvSRAM is shipped in a
preset state, best practice is to again rewrite the
nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently
(program bugs, incoming inspection routines,
etc.).
to “autostore enabled” on every power down
event captured by the nvSRAM. The application
firmware should disable autostore on each reset
sequence that this behavior is desired.
includes a minimum and a maximum value size.
Best practice is to meet this requirement and not
exceed the max V
internal algorithm calculates V
based on this max Vcap value. Customers that
want to use a larger V
there is extra store charge and store time should
discuss their V
understand any impact on the V
at the end of a t
=3.6V, and chip enable at maximum frequency.
1
2
3
4
5
6
cap
The duty cycle of chip enable
The overall cycle rate for operations
The ratio of READs to WRITEs
The operating temperature
The V
I/O Loading
value specified in this datasheet
cap
RECALL
CC
cap
size selection with Simtek to
Level
value because the nvSRAM
period.
Preliminary
cap
value to make sure
cap
cap
CC
voltage level
charge time
and READ/