stk14ee16 Simtek Corporation, stk14ee16 Datasheet - Page 12

• Manufacturer Part Number: stk14ee16
• Description: 512kx16 Autostore Nvsram
• Manufacturer: Simtek Corporation

Document Control #ML0069 Rev 1.0
STK14EE16
nvSRAM
The STK14EE16 nvSRAM is made up of two func-
tional components paired in the same physical cell.
These are the SRAM memory cell and a nonvolatile
QuantumTrap cell. The SRAM memory cell operates
like a standard fast static RAM. Data in the SRAM
can be transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to
SRAM (the RECALL operation). This unique archi-
tecture allows all cells to be stored and recalled in
parallel. During the STORE and RECALL operations
SRAM READ and WRITE operations are inhibited.
The STK14EE16 supports unlimited read and writes
like a typical SRAM. In addition, it provides unlimited
RECALL operations from the nonvolatile cells and
up to 1 million STORE operations.
SRAM READ
The STK14EE16 performs a READ cycle whenever
E and G are low while W and HSB are high. The
address specified on pins A
the 524,288 data words will be accessed. Byte
enables (UB, LB) determine which bytes are
enabled to the output. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of t
is initiated by E and G, the outputs will be valid at
t
#2). The data outputs will repeatedly respond to
address changes within the t
out the need for transitions on any control input pins,
and will remain valid until another address change
or until E or G is brought high, or W and HSB is
brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-15 will be written into memory if it is valid
t
t
Byte Enable inputs (UB, LB) determine which bytes
are written.
ELQV
DVWH
DVEH
March, 2008
before the end of an E controlled WRITE. The
or at t
before the end of a W controlled WRITE or
GLQV
AVQV
, whichever is later (READ cycle
(READ cycle #1). If the READ
0-18
AVQV
determine which of
access time with-
nvSRAM OPERATION
Simtek Confidential
12
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
low.
AutoStore OPERATION
The STK14EE16 stores data to nvSRAM using one
of three storage operations. These three operations
are Hardware Store (activated by HSB), Software
Store (activated by an address sequence), and
AutoStore (on power down).
AutoStore operation is a unique feature of Simtek
Quantum Trap technology that is enabled by default
on the STK14EE16.
During normal operation, the device will draw cur-
rent from V
the V
chip to perform a single STORE operation. If the
voltage on the V
part will automatically disconnect the V
V
provided by the V
Figure 3 shows the proper connection of the storage
capacitor (V
Refer to the DC CHARACTERISTICS table for the
size of the capacitor. The voltage on the V
driven to 3.6V by a regulator on the chip. A pull up
should be placed on W to hold it inactive during
power up.This pull-up is only effective if the W signal
CC
. A STORE operation will be initiated with power
v
CAP
CC
pin. This stored charge will be used by the
CC
CAP
Figure 3. AutoStore Mode
to charge a capacitor connected to
) for automatic store operation.
CC
CAP
pin drops below V
v
capacitor.
W
CC
Preliminary
WLQZ
v
CAP
after W goes
CAP
SWITCH
CAP
pin from
pin is
, the