m29dw256g Numonyx, m29dw256g Datasheet - Page 12

• Manufacturer Part Number: m29dw256g
• Description: 256-mbit X16, Multiple Bank, Page, Dual Boot 3 V Supply Flash Memory
• Manufacturer: Numonyx

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Signal descriptions
See
connected to this device.
Address inputs (A0-A23)
The address inputs select the cells in the memory array to access during bus read
operations. During bus write operations they control the commands sent to the command
interface of the program/erase controller.
Data inputs/outputs (DQ0-DQ15)
The data I/O outputs the data stored at the selected address during a bus read operation.
During bus write operations they represent the commands sent to the command interface of
the internal state machine. During bus write operations the command register does not use
DQ8-DQ15 bits that should be also ignored when reading the status register.
Chip enable (E)
The chip enable pin, E, activates the memory, allowing bus read and bus write operations to
be performed. When chip enable is High, V
Output enable (G)
The output enable pin, G, controls the bus read operation of the memory.
Write enable (W)
The write enable pin, W, controls the bus write operation of the memory’s command
interface.
V
The V
use an external high voltage power supply to reduce the time required for program
operations. This is achieved by bypassing the unlock cycles.
The write protect function provides a hardware method of protecting the four outermost
blocks, that is the two 32-kword blocks at the top and the two 32-kword blocks at the bottom
of the address space (see
When VPP/write protect is Low, VIL, the four outermost blocks are protected. Program and
erase operations on this block are ignored while VPP/write protect is Low.
PP
Figure 1: Logic
/write protect (V
PP
/write protect pin provides two functions. The V
diagram, and
1:
Description).
PP
/WP)
Table 3: Signal
IH
, all other pins are ignored.
names, for a brief overview of the signals
PPH
function allows the memory to