is45s16100c1 Integrated Silicon Solution, Inc., is45s16100c1 Datasheet - Page 31
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is45s16100c1
Manufacturer Part Number
is45s16100c1
Description
512k Words X 16 Bits X 2 Banks 16-mbit Synchronous Dynamic Ram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
1.IS45S16100C1.pdf
(81 pages)
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IS45S16100C1
Precharge
The precharge command sets the bank selected by pin A11
to the precharged state. This command can be executed at
a time t
the same bank. The selected bank goes to the idle state at
a time t
and an active command can be executed again for that
bank.
If pin A10 is low when this command is executed, the bank
selected by pin A11 will be precharged, and if pin A10 is
HIGH, both banks will be precharged at the same time. This
input to pin A11 is ignored in the latter case.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. C
01/03/06
CAS latency = 3, burstlength = 4
CAS latency = 2, burstlength = 4
RP
RAS
following the execution of the precharge command,
COMMAND
COMMAND
following the execution of an active command to
CLK
CLK
DQ
DQ
READ (CA=A, BANK 0)
READ (CA=A, BANK 0)
READ A0
READ A0
PRECHARGE (BANK 0)
D
OUT
A0 D
1-800-379-4774
D
PRE 0
PRE 0
OUT
OUT
Read Cycle Interruption
Using the Precharge Command
A read cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
command to the completion of the burst output is the
clock cycle of CAS latency.
A0 D
A1 D
PRECHARGE (BANK 0)
CAS
CAS
CAS
CAS
CAS Latency
t
RQL
OUT
OUT
t
RQL
A1 D
A2
t
RQL
RQL
) from the execution of the precharge
OUT
HI-Z
A2
HI-Z
3
3
ISSI
2
2
31
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