74LVQ74SCX Fairchild Semiconductor, 74LVQ74SCX Datasheet

74LVQ74SCX

Manufacturer Part Number

74LVQ74SCX

Description

IC FLIP FLOP DUAL D POS 14SOIC

Manufacturer

Fairchild Semiconductor

Series

74LVQr

Type

D-Typer

Datasheet

1.74LVQ74SJX.pdf (6 pages)

Specifications of 74LVQ74SCX

Function

Set(Preset) and Reset

Output Type

Differential

Number Of Elements

Number Of Bits Per Element

Frequency - Clock

125MHz

Delay Time - Propagation

8ns

Trigger Type

Positive Edge

Current - Output High, Low

12mA, 12mA

Voltage - Supply

2 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

14-SOIC (3.9mm Width), 14-SOL

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74LVQ74SC

74LVQ74SJ

74LVQ74

Low Voltage Dual D-Type

Positive Edge-Triggered Flip-Flop

General Description

The LVQ74 is a dual D-type flip-flop with Asynchronous

Clear and Set inputs and complementary (Q, Q) outputs.

Information at the input is transferred to the outputs on the

positive edge of the clock pulse. Clock triggering occurs at

a voltage level of the clock pulse and is not directly related

to the transition time of the positive-going pulse. After the

Clock Pulse input threshold voltage has been passed, the

Data input is locked out and information present will not be

transferred to the outputs until the next rising edge of the

Clock Pulse input.

Asynchronous Inputs:

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Order Number

LOW input to S

LOW input to C

Clear and Set are independent of clock

Simultaneous LOW on C

Q and Q HIGH

(Set) sets Q to HIGH level

(Clear) sets Q to LOW level

Package Number

IEEE/IEC

M14A

M14D

and S

makes both

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DS011347

Features

Connection Diagram

Pin Descriptions

Ideal for low power/low noise 3.3V applications

Guaranteed simultaneous switching noise level and

dynamic threshold performance

Guaranteed pin-to-pin skew AC performance

Guaranteed incident wave switching into 75

, D

, Q

, S

, C

, CP

, Q

Package Description

Pin Names

, Q

Data Inputs

Clock Pulse Inputs

Direct Clear Inputs

Direct Set Inputs

Outputs

February 1992

Revised June 2001

Description

www.fairchildsemi.com

Related parts for 74LVQ74SCX

74LVQ74SCX Summary of contents

Page 1

... Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC © 2001 Fairchild Semiconductor Corporation Features Ideal for low power/low noise 3.3V applications Guaranteed simultaneous switching noise level and ...

Page 2

Truth Table HIGH Voltage Level L LOW Voltage Level X Immaterial LOW-to-HIGH Clock Transition Previous Q(Q) before LOW-to-HIGH Transition of Clock 0 0 Logic Diagram Please note ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Input Voltage ( Output Diode Current ( ...

Page 4

AC Electrical Characteristics Symbol Parameter f Maximum Clock MAX Frequency t Propagation Delay PLH Propagation Delay PHL Propagation Delay PLH CP to ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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