lh28f160s5h-l Sharp Microelectronics of the Americas, lh28f160s5h-l Datasheet - Page 13

• Manufacturer Part Number: lh28f160s5h-l
• Description: M-bit Smart Flash Memories Fast Programming
• Manufacturer: Sharp Microelectronics of the Americas

4.1 Read Array Command
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, full chip erase, (multi) word/byte write
or block lock-bit configuration, the device will not
recognize the Read Array command until the WSM
completes its operation unless the WSM is
suspended via an Erase Suspend and (Multi)
Word/Byte Write Suspend command. The Read
Array command functions independently of the V
voltage and RP# must be V
4.2 Read Identifier Codes Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture, device, block
lock configuration and block erase status (see
Table 4 for identifier code values). To terminate the
operation, write another valid command. Like the
Read Array command, the Read Identifier Codes
command functions independently of the V
voltage and RP# must be V
Identifier Codes command, the following information
can be read :
Manufacture Code
Device Code
Block Status Code
• Block is Unlocked
• Block is Locked
• Last erase operation
• Last erase operation did
• Reserved for Future Use
completed successfully
not completed successfully
CODE
Table 4 Identifier Codes
IH
IH
X0004H
X0005H
.
. Following the Read
ADDRESS
00000H
00001H
00002H
00003H
(NOTE 1)
(NOTE 1)
DQ
DQ
DQ
DQ
DATA
DQ
D0
B0
0
0
1
1
2-7
= 0
= 1
= 0
= 1
PP
PP
- 13 -
NOTE :
1. X selects the specific block status code to be read. See
4.3 Read Status Register Command
The status register may be read to determine when
a block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration is complete and
whether the operation completed successfully (see
Table 13.1). It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
CE# (Either CE
or CE# (Either CE
before further reads to update the status register
latch. The Read Status Register command
functions independently of the V
must be V
The extended status register may be read to
determine multi byte write availability (see Table
13.2). The extended status register may be read at
any time by writing the Multi Byte Write command.
After writing this command, all subsequent read
operations output data from the extended status
register, until another valid command is written. The
contents of the extended status register are latched
on the falling edge of OE# or CE# (Either CE
CE
Multi Byte Write command must be re-issued to
update the extended status register latch.
4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 and SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 13.1).
By allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in
1
Fig. 2 for the device identifier code memory map.
#), whichever occurs last in the read cycle.
IH
.
0
# or CE
0
# or CE
1
#), whichever occurs. OE#
LH28F160S5-L/S5H-L
1
#) must toggle to V
PP
voltage. RP#
0
# or
IH