psd813f1a STMicroelectronics, psd813f1a Datasheet - Page 64

• Manufacturer Part Number: psd813f1a
• Description: Flash In-system Programmable Isp Peripherals For 8-bit Mcus, 5 V
• Manufacturer: STMicroelectronics

PSD813F1A
POWER MANAGEMENT
The PSD offers configurable power saving op-
tions. These options may be used individually or in
combinations, as follows:
–
–
64/111
All memory types in a PSD (Flash, EEPROM,
and SRAM) are built with Zero-Power
technology. In addition to using special silicon
design methodology, Zero-Power technology
puts the memories into standby mode when
address/data inputs are not changing (zero
DC current). As soon as a transition occurs on
an input, the affected memory “wakes up”,
changes and latches its outputs, then goes
back to standby. The designer does not have
to do anything special to achieve memory
standby mode when no inputs are changing—
it happens automatically.
The PLD sections can also achieve standby
mode when its inputs are not changing, as de-
scribed in the section entitled
Management, page
Like the Zero-Power feature, the Automatic
Power Down (APD) logic allows the PSD to
reduce to standby current automatically. The
APD will block MCU address/data signals from
reaching the memories and PLDs. This
feature is available on all PSD devices. The
APD Unit is described in more detail in the
sections entitled
(APD) Unit and Power-down Mode, page
Built in logic will monitor the address strobe of
the MCU for activity. If there is no activity for a
certain time period (MCU is asleep), the APD
logic initiates Power Down Mode (if enabled).
Once in Power Down Mode, all address/data
signals are blocked from reaching PSD
memories and PLDs, and the memories are
deselected internally. This allows the
memories and PLDs to remain in standby
mode even if the address/data lines are
Automatic Power-down
66.
PLD Power
65.
–
–
changing state externally (noise, other
devices on the MCU bus, etc.). Keep in mind
that any unblocked PLD input signals that are
changing states keeps the PLD out of standby
mode, but not the memories.
The PSD Chip Select Input (CSI) on all
families can be used to disable the internal
memories, placing them in standby mode
even if inputs are changing. This feature does
not block any internal signals or disable the
PLDs. This is a good alternative to using the
APD logic, especially if your MCU has a chip
select output. There is a slight penalty in
memory access time when the CSI signal
makes its initial transition from deselected to
selected.
The PMMR registers can be written by the
MCU at run-time to manage power. PSD
supports “blocking bits” in these registers that
are set to block designated signals from
reaching both PLDs. Current consumption of
the PLDs is directly related to the composite
frequency of the changes on their inputs (see
Figure 36., page 73
Significant power savings can be achieved by
blocking signals that are not used in DPLD or
CPLD logic equations.
The PSD has a Turbo Bit in the PMMR0
register. This bit can be set to disable the
Turbo Mode feature (default is Turbo Mode
on). While Turbo Mode is disabled, the PLDs
can achieve standby current when no PLD
inputs are changing (zero DC current). Even
when inputs do change, significant power can
be saved at lower frequencies (AC current),
compared to when Turbo Mode is enabled.
When the Turbo Mode is enabled, there is a
significant DC current component and the AC
component is higher.
and
Figure 37., page
73).