m58lw064c STMicroelectronics, m58lw064c Datasheet - Page 6

• Manufacturer Part Number: m58lw064c
• Description: 64 Mbit 4mb X16, Uniform Block, Burst 3v Supply Flash Memory
• Manufacturer: STMicroelectronics

M58LW064C
SUMMARY DESCRIPTION
M58LW064C is a 64 Mbit (4Mb x16) non-volatile
memory that can be read, erased and repro-
grammed. These operations can be performed us-
ing a single low voltage (2.7V to 3.6V) core supply.
On power-up the memory defaults to Read mode
with an asynchronous bus where it can be read in
the same way as a non-burst Flash memory.
The memory is divided into 64 blocks of 1Mbit that
can be erased independently so it is possible to
preserve valid data while old data is erased. Pro-
gram and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a program or erase operation can be detected and
any error conditions identified in the Status Regis-
ter. The command set required to control the
memory is consistent with JEDEC standards.
The device supports synchronous burst read and
asynchronous read from all blocks of the memory
array; at power-up the device is configured for
asynchronous read. In asynchronous mode an
Address Latch input can be used to latch address-
es in Latch Controlled mode. In synchronous burst
mode, data is output on each clock cycle at fre-
quencies of up to 56MHz.
The Write Buffer allows the microprocessor to pro-
gram from 1 to 16 Words in parallel, both speeding
up the programming and freeing up the micropro-
cessor to perform other work. A Word Program
command is available to program a single Word.
Erase can be suspended in order to perform either
Read or Program in any other block and then re-
sumed. Program can be suspended to read data in
any other block and then resumed. Each block can
be programmed and erased over 100,000 cycles.
The M58LW064C has several security features to
increase data protection.
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Block Protection, where each block can be
individually protected against program or
erase operations. All blocks are protected
during power-up. The protection of the blocks
The Reset/Power-Down pin is used to apply a
Hardware Reset to the memory and to set the de-
vice in power-down mode.
The device features an Auto Low Power mode. If
the bus becomes inactive during Asynchronous
Read operations, the device automatically enters
Auto Low Power mode. In this mode the power
consumption is reduced to the Auto Low Power
supply current.
The STS signal is an open drain output that can be
used to identify the Program/Erase Controller sta-
tus. It can be configured in two modes: Ready/
Busy mode where a static signal indicates the sta-
tus of the P/E.C, and Status mode where a pulsing
signal indicates the end of a Program or Block
Erase operation. In Status mode it can be used as
a system interrupt signal, useful for saving CPU
time.
The memory is available in TSOP56 (14 x 20 mm)
and TBGA64 (10 x 13mm, 1mm pitch) packages.
In addition to the standard version, the packages
are also available in Lead-free version, in compli-
ance with JEDEC Std J-STD-020B, the ST ECO-
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
is non-volatile; after power-up the protection
status of each block is restored to the state
when power was last removed.
Program Erase Enable input V
erase operations are not possible when the
Program Erase Enable input V
Smart Protection, which allows protected
blocks to be permanently locked. This feature
is not described in the datasheet for security
reasons. Please contact STMicroelectronics
for further details.
128 bit Protection Register, divided into two 64
bit segments: the first contains a unique
device number written by ST, the second is
user programmable. The user programmable
segment can be protected.
PEN
PEN
, program or
is low.