w9425g6dh Winbond Electronics Corp America, w9425g6dh Datasheet - Page 14

• Manufacturer Part Number: w9425g6dh
• Description: 4m X 4 Banks X 16 Bits Ddr Sdram
• Manufacturer: Winbond Electronics Corp America

7.9
DDR SDRAM input clock frequency can be changed under following condition:
DDR SDRAM must be in precharged power down mode with CKE at logic LOW level. After a minimum
of 2 clocks after CKE goes LOW, the clock frequency may change to any frequency between minimum
and maximum operating frequency specified for the particular speed grade. During an input clock
frequency change, CKE must be held LOW. Once the input clock frequency is changed, a stable clock
must be provided to DRAM before precharge power down mode may be exited. The DLL must be
RESET via EMRS after precharge power down exit. An additional MRS command may need to be
issued to appropriately set CL etc. After the DLL relock time, the DRAM is ready to operate with new
clock frequency.
7.10 Mode Register Operation
The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks
are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A12 and
BS0, BS1 address inputs.
The Mode Register designates the operation mode for the read or write cycle. The register is divided
into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to
designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time in
clock cycle (4) DLL reset field to reset the DLL (5) Regular/Extended Mode Register filed to select a
type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL
enable/Disable mode)
The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the
Mode Register Set command must be issued before power operation.
7.10.1 Burst Length field (A2 to A0)
7.10.2 Addressing Mode Select (A3)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst
Length to be 2, 4, and 8 words.
The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the
A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both
addressing Mode support burst length 2, 4, and 8 words.
Input Clock Frequency Change during Precharge Power Down Mode
A2
A3
0
0
0
0
1
0
1
A1
0
0
1
1
x
A0
0
1
0
1
x
ADDRESSING MODE
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Sequential
Interleave
Publication Release Date:Feb. 12, 2008
BURST LENGTH
Reserved
Reserved
2 words
4 words
8 words
W9425G6DH
Revision A8