cy62256ll-55ze Cypress Semiconductor Corporation., cy62256ll-55ze Datasheet

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cy62256ll-55ze

Manufacturer Part Number
cy62256ll-55ze
Description
256k 32k X 8 Static Ram
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Part Number:
CY62256LL-55ZE
Manufacturer:
CY
Quantity:
5 530
Cypress Semiconductor Corporation
Document #: 38-05248 Rev. *F
Features
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
• High speed
• Temperature Ranges
• Voltage range
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in a Pb-free and non Pb-free standard 28-pin
Logic Block Diagram
— 55 ns
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
— 4.5V – 5.5V
narrow SOIC, 28-pin TSOP-1, 28-pin Reverse TSOP-1
and 28-pin DIP packages
CE
WE
OE
A
A
A
A
A
A
A
A
A
10
9
8
7
6
5
4
3
2
198 Champion Court
INPUTBUFFER
DECODER
32K × 8
ARRAY
COLUMN
Functional Description
The CY62256 is a high-performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and Tri-state drivers. This device has an
automatic
consumption by 99.9% when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
addressed by the address present on the address pins (A
through A
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
POWER
DOWN
0
through I/O
256K (32K x 8) Static RAM
14
San Jose
). Reading the device is accomplished by selecting
power-down
7
) is written into the memory location
,
CA 95134-1709
feature,
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
[1]
0
1
2
3
4
5
6
7
Revised August 3, 2006
reducing
CY62256
408-943-2600
the
power
0
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cy62256ll-55ze Summary of contents

Page 1

... Document #: 38-05248 Rev. *F 256K (32K x 8) Static RAM Functional Description The CY62256 is a high-performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and Tri-state drivers. This device has an automatic power-down consumption by 99 ...

Page 2

... Product Portfolio Product Min. CY62256L Com’l/Ind’l 4.5 CY62256LL Commercial CY62256LL Industrial CY62256LL Automotive Pin Configurations Narrow SOIC Top View ...

Page 3

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ...

Page 4

AC Test Loads and Waveforms R1 1800Ω 5V OUTPUT OUTPUT R2 100 pF 990Ω INCLUDING JIG AND SCOPE (a) Equivalent to: Data Retention Characteristics Parameter Description V V for Data Retention Data Retention Current CCDR [5] t ...

Page 5

... L 10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write. ...

Page 6

Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) ADDRESS DATA OUT PREVIOUS DATA VALID [13, 14] Read Cycle No. 2 (OE Controlled ACE OE t LZOE HIGH IMPEDANCE DATA OUT t LZCE SUPPLY ...

Page 7

Switching Waveforms (continued) [10, 15, 16] Write Cycle No. 2 (CE Controlled) ADDRESS CE WE DATA I/O Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS DATA I/O NOTE 17 t HZWE Document #: 38-05248 Rev. ...

Page 8

Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1 1.0 0 25°C A 0.4 0 0.0 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) NORMALIZED ...

Page 9

Typical DC and AC Characteristics TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 SUPPLY VOLTAGE (V) Truth Table Inputs/Outputs High ...

Page 10

... CY62256LL−70PC CY62256LL−70PXC CY62256L−70SNC CY62256L−70SNXC CY62256LL−70SNC CY62256LL−70SNXC CY62256LL−70ZC CY62256LL−70ZXC CY62256L–70SNI CY62256L–70SNXI CY62256LL−70SNI CY62256LL−70SNXI CY62256LL−70ZXI CY62256LL−70ZRI CY62256LL−70ZRXI Please contact your local Cypress sales representative for availability of these parts Document #: 38-05248 Rev ...

Page 11

Package Diagrams 28-pin (600-mil) Molded DIP (51-85017 0.155 0.200 0.115 0.160 0.090 0.110 28-pin (300-mil) SNC (Narrow Body) (51-85092) Document #: 38-05248 Rev 0.530 0.550 28 0.070 0.090 SEATING PLANE 1.380 1.480 0.140 0.195 0.015 0.060 ...

Page 12

Package Diagrams (continued) 28-pin Thin Small Outline Package Type 13.4 mm) (51-85071) Document #: 38-05248 Rev. *F CY62256 51-85071-*G Page [+] Feedback ...

Page 13

Package Diagrams (continued) 28-pin Reverse Thin Small Outline Package Type 1 (8x13.4 mm) (51-85074) All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05248 Rev. *F © Cypress Semiconductor Corporation, 2006. ...

Page 14

Document History Page Document Title: CY62256, 256K (32K x 8) Static RAM Document Number: 38-05248 Issue Orig. of REV. ECN NO. Date Change ** 113454 03/06/02 MGN *A 115227 05/23/02 GBI *B 116506 09/04/02 GBI *C 238448 See ECN AJU ...

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