cy62128v18ll-200zri Cypress Semiconductor Corporation., cy62128v18ll-200zri Datasheet
cy62128v18ll-200zri
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cy62128v18ll-200zri Summary of contents
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... Reading from the device is accomplished by taking Chip Enable 1 (CE 1 Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O high-impedance state when the device is deselected (CE ...
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Pin Configurations Top View SOIC DNU DNU ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential .......................................................... −0.3V to 3.9V DC ...
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AC Test Loads and Waveforms OUTPUT 50 pF INCLUDING JIG AND SCOPE Parameters Data Retention Characteristics Parameter Description V V for Data Retention Data Retention Current CCDR [4] ...
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... HZOE HZCE HZBE HZWE 12. The internal write time of the memory is defined by the overlap of WE, CE 13. Device is continuously selected HIGH for Read cycle. Document #: 38-05231 Rev. *H [9] CY62128DV30-55 Description Min ...
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Switching Waveforms (continued) [11, 14, 15] Read Cycle No. 2 (OE Controlled) ADDRESS ACE OE t LZOE HIGH IMPEDANCE DATA OUT t LZCE SUPPLY CURRENT [12, 16, 17, 18] Write Cycle ...
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Switching Waveforms (continued) Write Cycle No Controlled ADDRESS DATA I/O Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS DON'T CARE DATA ...
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Ordering Information Speed (ns) Ordering Code 55 CY62128DV30L-55SI CY62128DV30LL-55SI CY62128DV30LL-55SXI CY62128DV30L-55ZI CY62128DV30LL-55ZI CY62128DV30LL-55ZXI CY62128DV30L-55ZAI CY62128DV30LL-55ZAI CY62128DV30LL-55ZAXI CY62128DV30L-55ZRI CY62128DV30LL-55ZRI CY62128DV30LL-55ZRXI 70 CY62128DV30L-70SI CY62128DV30LL-70SI CY62128DV30LL-70SXI CY62128DV30L-70ZI CY62128DV30LL-70ZI CY62128DV30LL-70ZXI CY62128DV30L-70ZAI CY62128DV30LL-70ZAI CY62128DV30LL-70ZAXI CY62128DV30L-70ZRI CY62128DV30LL-70ZRI Document #: 38-05231 Rev. *H Package Diagram Package Type ...
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Package Diagrams 32 LD (450 Mil) SOIC 16 17 0.793[20.142] 0.817[20.751] 0.101[2.565] 0.111[2.819] 0.050[1.270] BSC. 0.014[0.355] 0.020[0.508] 32-Lead TSOP Type mm) (51-85056) Document #: 38-05231 Rev. *H 32-Lead (450-Mil) SOIC (51-85081) 1 0.546[13.868] 0.566[14.376] 0.440[11.176] DIMENSIONS ...
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... Package Diagrams (continued) MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05231 Rev. *H © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...
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Document History Page Document Title: CY62128DV30 1-Mb (128K x 8) Static RAM Document Number: 38-05231 Orig. of REV. ECN NO. Issue Date Change ** 117691 08/27/02 *A 127314 5/27/03 *B 128342 07/23/03 *C 129002 08/29/03 *D 347394 See ECN *E ...