m45pe40 STMicroelectronics, m45pe40 Datasheet - Page 31

• Manufacturer Part Number: m45pe40
• Description: 4 Mbit, Low Voltage, Page-erasable Serial Flash Memory With Byte-alterability And A 50 Mhz Spi Bus Interface
• Manufacturer: STMicroelectronics

M45PE40
7
Power-up and power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V
A safe configuration is provided in
To avoid data corruption and inadvertent write operations during power up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while V
than the Power On Reset (POR) threshold voltage, V
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program
(PP), Page Erase (PE) and Sector Erase (SE) instructions until a time delay of t
elapsed after the moment that V
operation of the device is not guaranteed if, by this time, V
Write, Program or Erase instructions should be sent until the later of:
These values are specified in
If the delay, t
selected for READ instructions even if the t
As an extra protection, the Reset (Reset) signal can be driven Low for the whole duration of
the Power-up and Power-down phases.
At Power-up, the device is in the following state:
Normal precautions must be taken for supply rail decoupling, to stabilize the V
Each device in a system should have the V
the package pins. (Generally, this capacitor is of the order of 100 nF).
At Power-down, when V
(POR) threshold voltage, V
to any instruction. (The designer needs to be aware that if a Power-down occurs while a
Write, Program or Erase cycle is in progress, some data corruption can result.)
V
V
t
t
The device is in the Standby Power mode (not the Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
The Write In Progress (WIP) bit is reset.
PUW
VSL
CC
SS
(min) at Power-up, and then for a further delay of t
at Power-down
after V
after V
VSL
, has elapsed, after V
CC
CC
passed the V
passed the V
CC
WI
drops from the operating voltage, to below the Power On Reset
, all operations are disabled and the device does not respond
Table
CC
CC
CC
) until V
WI
Section 3: SPI
(min) level
rises above the V
6.
threshold
CC
has risen above V
CC
CC
PUW
reaches the correct value:
rail decoupled by a suitable capacitor close to
delay is not yet fully elapsed.
modes.
WI
WI
– all operations are disabled, and
threshold. However, the correct
CC
CC
VSL
is still below V
(min), the device can be
Power-up and power-down
CC
CC
(min). No
PUW
CC
supply.
is less
has
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