m95320 STMicroelectronics, m95320 Datasheet - Page 10

no-image

m95320

Manufacturer Part Number
m95320
Description
32 Kbit And 64 Kbit Serial Spi Bus Eeproms With High Speed Clock
Manufacturer
STMicroelectronics
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M95320
Manufacturer:
ST
0
Part Number:
m95320 3
Manufacturer:
ST
0
Part Number:
m95320 6
Manufacturer:
ST
0
Part Number:
m95320 Q
Manufacturer:
ST
0
Part Number:
m95320-BN3TP
Manufacturer:
ST
0
Part Number:
m95320-DRMF3TG/K
Manufacturer:
ST
Quantity:
20 000
Part Number:
m95320-DRMN3TP/K
Manufacturer:
ST
Quantity:
20 000
Part Number:
m95320-DRMN3TP/K
0
Company:
Part Number:
m95320-DRMN3TP/K
Quantity:
626
Connecting to the SPI bus
3
10/45
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such
as the Read from Memory Array and Read Status Register instructions) have been clocked
into the device.
Figure 3
selected at a time, so only one device drives the Serial Data output (Q) line at a time, all the
others being high impedance.
Figure 3.
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
The pull-up resistor R (represented in
bus master leaves the S line in the high impedance state.
In applications where the bus master might enter a state where all inputs/outputs SPI bus
would be in high impedance at the same time (for example, if the bus master is reset during
the transmission of an instruction), the clock line (C) must be connected to an external pull-
down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high): this will ensure that S and C do not become high at the
same time, and so, that the t
CS3
SPI interface with
(CPOL, CPHA) =
SPI bus master
(0, 0) or (1, 1)
CS2
shows three devices, connected to an MCU, on a SPI bus. Only one device is
Bus master and memory devices on the SPI bus
CS1
SDO
SDI
SCK
R
R
SHCH
C Q D
S
SPI memory
device
requirement is met. The typical value of R is 100 kΩ.
W
Figure
V
CC
HOLD
V
3) ensures that a device is not selected if the
SS
R
C Q D
M95320, M95640, M95320-x, M95640-x
S
SPI memory
device
W
V
HOLD
CC
V
SS
R
C Q D
S
SPI memory
device
W
V
CC
HOLD
AI12836b
V
SS
V
V
CC
SS

Related parts for m95320