is42s32160c Integrated Silicon Solution, Inc., is42s32160c Datasheet - Page 8

• Manufacturer Part Number: is42s32160c
• Description: 16mx32 512mb Synchronous Dram
• Manufacturer: Integrated Silicon Solution, Inc.

IS42S32160C
8
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write command.The
DQMs must be asserted (HIGH)at least two clocks prior to the Write command to suppress data-out on the DQ pins.To
guarantee the DQ pins against I/O contention,a single cycle with high-impedance on the DQ pins must occur between the
last read data and the Write command (refer to the following three figures).If the data output of the burst read occurs at the
second clock of the burst write,the DQMs must be asserted (HIGH)at least one clock prior to the Write command to avoid
internal bus contention.
CAS# latency=2
t CK2 , DQ- s
CLK
COMMAND
CAS# latency=3
t CK3 , DQ- s
Read Interrupted by a Read (Burst Length =4,CAS#Latency =2,3)
READ A
T0
READ B
T1
DOUT A 0
T2
NOP
DOUT B 0
NOP
T3
DOUT A 0
DOUT B 0
NOP
T4
DOUT B 1
NOP
DOUT B 2
T5
DOUT B 1
NOP
T6
DOUT B 3
DOUT B
Integrated Silicon Solution, Inc.
2
T7
NOP
DOUT B 3
NOP
T8
Rev. B
01/22/09