is42s16800al-7tli Integrated Silicon Solution, Inc., is42s16800al-7tli Datasheet - Page 2

• Manufacturer Part Number: is42s16800al-7tli
• Description: 128-mbit Low-power Synchronous Dram
• Manufacturer: Integrated Silicon Solution, Inc.

DEVICE OVERVIEW
The 128Mb Low - Power SDRAM is a high speed CMOS,
dynamic random-access memory designed to operate in
2.5V V
systems containing 134,217 ,728 bits. Internally configured
as a quad-bank DRAM with a synchronous interface. (Each
33,554,432-bit bank is organized as 4,096 rows by 512
columns by 16 bits.)
The 128Mb Low - Power SDRAM includes an AUTO RE-
FRESH MODE, and a power-saving, power-down mode.
All signals are registered on the positive edge of the clock
signal, CLK. All inputs and outputs are LVTTL compatible.
Only partials of the memory array can be selected for Self-
Refresh and the refresh period during Self-Refresh is
programmable in 4 steps which drastically reduces the self
refresh current, depending on the case temperature of the
components in the system application.
The 128Mb Low - Power SDRAM has the ability to synchro-
nously burst data at a high data rate with automatic column-
address generation, the ability to interleave between inter-
FUNCTIONAL BLOCK DIAGRAM (ONLY FOR 2MX16X4 BANKS)
IS42S81600AL, IS42S16800AL, IS42S32400AL
IS42LS81600AL, IS42LS16800AL, IS42LS32400AL
2
DD
CKE
RAS
CAS
A10
CLK
BA0
BA1
A11
WE
CS
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
and 1.8V V
GENERATOR
COMMAND
DECODER
12
CLOCK
&
DDQ
ADDRESS
LATCH
ROW
or 3.3VV
9
ADDRESS BUFFER
BURST COUNTER
ADDRESS LATCH
REGISTER
MODE
COLUMN
COLUMN
DD
12
and 3.3V V
Integrated Silicon Solution, Inc. — www.issi.com —
DDQ
memory
12
CONTROLLER
COUNTER
REFRESH
REFRESH
CONTROLLER
REFRESH
ADDRESS
BUFFER
SELF
ROW
nal banks to hide precharge time and the capability to
randomly change column addresses on each clock cycle
during burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE func-
tion enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting at
a selected location and continuing for a programmed num-
ber of locations in a programmed sequence. The registra-
tion of an ACTIVE command begins accesses, followed by
a READ or WRITE command. The ACTIVE command in
conjunction with address bits registered are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A11 select the row). The READ or WRITE
commands in conjunction with address bits registered are
used to select the starting column location for the burst
access.
Programmable READ or WRITE burst lengths consist of 1,
2, 4 and 8 locations or full page, with a burst terminate
option.
BANK CONTROL LOGIC
12
PRELIMINARY
4096
16
16
4096
4096
4096
DATA OUT
BUFFER
BUFFER
9
DATA IN
(x 16)
512
COLUMN DECODER
SENSE AMP I/O GATE
MEMORY CELL
BANK 0
16
16
ARRAY
2
INFORMATION
DQML
DQMH
I/O 0-15
ISSI
V
V
DD
ss
1-800-379-4774
/V
/V
ss
DDQ
Q
Rev. 00A
09/18/03
®