at28bv16 ATMEL Corporation, at28bv16 Datasheet - Page 3
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at28bv16
Manufacturer Part Number
at28bv16
Description
Battery-voltage Cmos
Manufacturer
ATMEL Corporation
Datasheet
1.AT28BV16.pdf
(8 pages)
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Quantity
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Manufacturer:
TOSHIBA
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Device Operation
READ:
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in a high im-
pedance state whenever CE or OE is high. This dual line
control gives designers increased flexibility in preventing
bus contention.
BYTE WRITE:
to writing into a Static RAM. A low pulse on the WE or CE
input with OE high and CE or WE low (respectively) initi-
ates a byte write. The address location is latched on the
last falling edge of WE (or CE); the new data is latched on
the first rising edge. Internally, the device performs a self-
clear before write. Once a byte write has been started, it
will automatically time itself to completion. Once a pro-
gramming operation has been initiated and for the dura-
tion of t
operation.
DATA POLLING:
POLLING to signal the completion of a write cycle. During
a write cycle, an attempted read of the data being written
results in the complement of that data for I/O
outputs are indeterminate). When the write cycle is fin-
ished, true data appears on all outputs.
WC
The AT28BV16 is accessed like a Static RAM.
, a read operation will effectively be a polling
Writing data into the AT28BV16 is similar
The AT28BV16 provides DATA
7
(the other
READY/BUSY (TSOP only):
drain output; it is pulled low during the internal write cycle
and released at the completion of the write cycle.
WRITE PROTECTION:
are protected against in the following ways. (a) Vcc
sense— if Vcc is below 2.0V (typical) the write function is
inhibited. (b) Vcc power on delay— once Vcc has reached
2.0V the device will automatically time out 5 ms (typical)
before allowing a byte write. (c) Write Inhibit— holding any
one of OE low, CE high or WE high inhibits byte write cy-
cles.
DEVICE IDENTIFICATION:
E
identification. By raising A9 to 12
dress locations 7E0H to 7FFH the additional bytes may be
written to or read from in the same manner as the regular
memory array.
2
PROM memory are available to the user for device
AT28BV16
Inadvertent writes to the device
READY/BUSY is an open
A n ex t r a 32- bytes of
0.5V and using ad-
2-121