at49sn6416 ATMEL Corporation, at49sn6416 Datasheet - Page 5

• Manufacturer Part Number: at49sn6416
• Description: 64-megabit 4m X 16 Burst/page Mode 1.8-volt Flash Memory
• Manufacturer: ATMEL Corporation

3.6
3.7
3464C–FLASH–2/05
Continuous Burst Read
Fixed-length Burst Reads
During a continuous burst read, any number of addresses can be read from the memory. When
operating in the linear burst read mode (B7 = 1) with the burst wrap bit (B3 = 1) set, the device
may incur an output delay when the burst sequence crosses the first 16-word boundary in the
memory (see
or D12), there is no delay. If the starting address is not aligned with a 4-word boundary, an out-
put delay is incurred. The delay depends on the starting address (see
takes place only once, and only if the burst sequence crosses a 16-word boundary. To indicate
that the device is not ready to continue the burst, the device will drive the WAIT pin low (B10 and
B8 = 0) during the clock cycles in which new data is not being presented. Once the WAIT pin is
driven high (B10 and B8 = 0), the current data will be valid. The WAIT signal will be tri-stated
when the CE or OE signal is high.
Table 3-1.
In the
the specified clock latency of four, data D11 is valid within 13 ns of clock edge B. The low-to-high
transition of the clock at point C results in D12 being read. The transition of the clock at point D
results in a burst read of D15. The clock transition at point E does not cause new data to appear
on the output lines because the WAIT signal goes low (B10 and B8 = 0) after the clock transition,
which signifies that the first boundary in the memory has been crossed and that new data is not
available. The clock transition at point F does cause a burst read of data D16 because the WAIT
signal goes high (B10 and B8 = 0) after the clock transition indicating that new data is available.
Additional clock transitions, like at point G, will continue to result in burst reads.
During a fixed-length burst mode read, four, eight or sixteen words of data may be burst from the
device, depending upon the configuration. The device supports a linear burst mode. The burst
sequence is shown on
burst wrap bit (B3 = 1) set, the device may incur an output delay when the burst sequence
crosses the first 16-word boundary in the memory. If the starting address is aligned with a
4-word boundary (D0, D4, D8 or D12), there is no delay. If the starting address is not aligned
with a 4-word boundary an output delay is incurred. The delay depends on the starting address
(see
16-word boundary. To indicate that the device is not ready to continue the burst, the device will
drive the WAIT pin low (B10 and B8 = 0) during the clock cycles in which new data is not being
presented. Once the WAIT pin is driven high (B10 and B8 = 0), the current data will be valid. The
WAIT signal will be tri-stated when the CE or OE signal is high.
The
valid address is latched at point A. For the specified clock latency of four, data D0 is valid within
13 ns of clock edge B. The low-to-high transition of the clock at point C results in D1 being read.
Similarly, D2 and D3 are output following the next two clock cycles. Returning CE high ends the
read cycle. There is no output delay in the burst access wrap mode (B3 = 0).
Starting Address
D1, D5, D9, D13
D2, D6, D10, D14
D3, D7, D11, D15
“Four-word Burst Read Waveform”
Table
“Burst Read Waveform”
3-1). The delay takes place only once, and only if the burst sequence crosses a
Figure
Output Delay
3-1). If the starting address is aligned with a 4-word boundary (D0, D4, D8
Output Delay
Hold Data for 1 Clock Cycle, B9 = 0
1 Clock Cycle
2 Clock Cycles
3 Clock Cycles
page
22. When operating in the linear burst read mode (B7 = 1) with the
as shown on
on
page
page 33
32, the valid address is latched at point A. For
illustrates a fixed-length burst cycle. The
Output Delay
Hold Data for 2 Clock Cycles, B9 = 1
2 Clock Cycle
4 Clock Cycles
6 Clock Cycles
AT49SN6416(T)
Table
3-1). The delay
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