at49sn6416 ATMEL Corporation, at49sn6416 Datasheet - Page 4

• Manufacturer Part Number: at49sn6416
• Description: 64-megabit 4m X 16 Burst/page Mode 1.8-volt Flash Memory
• Manufacturer: ATMEL Corporation

3.3
3.4
3.5
4
Asynchronous Read
Page Read
Synchronous Reads
AT49SN6416(T)
There are two types of asynchronous reads – AVD pulsed and standard asynchronous reads.
The AVD pulsed read operation of the device is controlled by CE, OE, and AVD inputs. The out-
puts are put in the high-impedance state whenever CE or OE is high. This dual-line control gives
designers flexibility in preventing bus contention. The data at the address location defined by
A0 - A21 and captured by the AVD signal will be read when CE and OE are low. The address
location passes into the device when CE and AVD are low; the address is latched on the low-to-
high transition of AVD. Low input levels on the OE and CE pins allow the data to be driven out of
the device. The access time is measured from stable address, falling edge of AVD or falling
edge of CE, whichever occurs last. During the AVD pulsed read, the CLK signal may be static
high or static low. For standard asynchronous reads, the AVD and CLK signal should be tied to
GND. The asynchronous read diagrams are shown on
The page read operation of the device is controlled by CE, OE, and AVD inputs. The CLK input
is ignored during a page read operation and should be tied to GND. The page size is four words.
During a page read, the AVD signal can transition low and then transition high, transition low and
remain low, or can be tied to GND. If a high to low transition on the AVD signal occurs, as shown
in Page Read Cycle Waveform 1, the page address is latched by the low-to-high transition of the
AVD signal. However, if the AVD signal remains low after the high-to-low transition or if the AVD
signal is tied to GND, as shown in Page Read Cycle Waveform 2, then the page address (deter-
mined by A21 - A2) cannot change during a page read operation. The first word access of the
page read is the same as the asynchronous read. The first word is read at an asynchronous
speed of 70 ns. Once the first word is read, toggling A0 and A1 will result in subsequent reads
within the page being output at a speed of 20 ns. If the AVD and the CLK pins are both tied to
GND, the device will behave like a standard asynchronous Flash memory. The page read dia-
grams are shown on
Synchronous reads are used to achieve a faster data rate than is possible in the asynchro-
nous/page read mode. The device can be configured for continuous or fixed-length burst
access. The burst read operation of the device is controlled by CE, OE, CLK and AVD inputs.
The initial read location is determined as for the AVD pulsed asynchronous read operation; it can
be any memory location in the device. In the burst access, the address is latched on the first
valid clock edge when AVD is low or the rising edge of the AVD signal, whichever occurs first.
The CLK input signal controls the flow of data from the device for a burst operation. After the
clock latency cycles, the data at the next burst address location is read for each following clock
cycle.
Figure 3-1.
D0 D1
Word Boundary
Word D0 - D3
page
D2
D3 D4
30.
Word D4 - D7
D5
4-word Boundary
D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
Word D8 - D11
page
29.
Word D12 - D15
16-word Boundary
3464C–FLASH–2/05