at49sv322a ATMEL Corporation, at49sv322a Datasheet - Page 9

• Manufacturer Part Number: at49sv322a
• Description: 32-megabit 2m X 16/4m X 8 1.8-volt Only Flash Memory
• Manufacturer: ATMEL Corporation

4.13
4.14
4.15
4.16
3360E–FLASH–10/05
RDY/BUSY
Common Flash Interface (CFI)
Hardware Data Protection
Input Levels
For the AT49SV322A(T), an open-drain READY/BUSY output pin provides another method of
detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the
internal program and erase cycles and is released at the completion of the cycle. The open-drain
connection allows for OR-tying of several devices to the same RDY/BUSY line. See
Table” on page 12
CFI is a published, standardized data structure that may be read from a flash device. CFI allows
system software to query the installed device to determine the configurations, various electrical
and timing parameters, and functions supported by the device. CFI is used to allow the system
to learn how to interface to the flash device most optimally. The two primary benefits of using
CFI are ease of upgrading and second source availability. The command to enter the CFI Query
mode is a one-bus cycle command which requires writing data 98h to address 55h. The CFI
Query command can be written when the device is ready to read data or can also be written
when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI
data at the addresses given in
the CFI Query mode, the product ID exit command must be given.
The Hardware Data Protection feature protects against inadvertent programs to the
AT49SV322A(T) in the following ways: (a) V
gram function is inhibited. (b) V
the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE low, CE high or WE high inhibits program cycles. (d) Program inhibit: V
is less than V
ations are inhibited for 100 ns.
While operating with a 1.65V to 1.95V power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the
device. The I/O lines can only be driven from 0 to V
ILPP
. (e) V
for more details.
PP
power-on delay: once V
“Common Flash Interface Definition Table” on page
CC
power-on delay: once V
CC
sense: if V
PP
CC
has reached 0.9V, program and erase oper-
+ 0.6V.
CC
CC
has reached the V
is below 1.65V (typical), the pro-
AT49SV322A(T)
CC
sense level,
27. To exit
“Status Bit
PP
9