74aup1g98gw NXP Semiconductors, 74aup1g98gw Datasheet
74aup1g98gw
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74aup1g98gw Summary of contents
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Low-power configurable multiple function gate Rev. 01 — 8 November 2006 1. General description The 74AUP1G98 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. This device ensures a very low static ...
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... Temperature range Name 74AUP1G98GW +125 C 74AUP1G98GM +125 C 74AUP1G98GF +125 C 4. Marking Table 2. Marking Type number 74AUP1G98GW 74AUP1G98GM 74AUP1G98GF 5. Functional diagram Fig 1. Logic symbol 74AUP1G98_1 Product data sheet Low-power configurable multiple function gate Description SC-88 plastic surface-mounted package; 6 leads XSON6 plastic extremely thin small outline package ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning 74AUP1G98 GND 001aad988 Fig 2. Pin configuration SOT363 (SC-88) 6.2 Pin description Table 3. Pin description Symbol Pin B 1 GND Functional description [1] Table 4. Function table Input ...
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... NXP Semiconductors 7.1 Logic configurations Table 5. Function selection table Logic function 2-input MUX with inverted output 2-input NAND 2-input NOR with one input inverted 2-input AND with one input inverted 2-input NAND with one input inverted 2-input OR with one input inverted ...
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... NXP Semiconductors Fig 11. Inverter 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current output voltage ...
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... NXP Semiconductors 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter amb V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF I additional power-off OFF leakage current ...
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... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF I additional power-off OFF leakage current I supply current CC I additional supply current +125 C ...
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... NXP Semiconductors Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional power-off OFF leakage current I supply current CC I additional supply current CC [1] One input at V 0.6 V, other input 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see ...
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... NXP Semiconductors Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation delay see pF and power dissipation MHz capacitance [1] All typical values are measured at nominal V ...
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... NXP Semiconductors 12. Waveforms input Measurement points are given in V and V are typical output voltage drop that occur with the output load Fig 12. Input A, B and C to output Y propagation delay times. Table 10. Measurement points Supply voltage Output 0 3.6 V ...
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... NXP Semiconductors Test data is given in Table 11. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 13. Load circuitry for switching times Table 11 ...
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... NXP Semiconductors Table 12. Transfer characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Symbol Parameter Conditions V hysteresis ( voltage Figure Figure 14. Waveforms transfer characteristics Fig 14. Transfer characteristic 74AUP1G98_1 Product data sheet … ...
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... NXP Semiconductors Fig 16. Typical transfer characteristics; V Fig 17. Typical transfer characteristics; V 74AUP1G98_1 Product data sheet Low-power configurable multiple function gate 240 160 0.4 0.8 1 1200 800 400 0 0 1.0 2 Rev. 01 — 8 November 2006 74AUP1G98 001aad691 1.6 2.0 V (V) I 001aad692 3.0 V (V) I © NXP B.V. 2006. All rights reserved. ...
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... NXP Semiconductors 15. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 0.30 1.1 0.25 mm 0.1 0.20 0.8 0.10 OUTLINE VERSION IEC SOT363 Fig 18. Package outline SOT363 (SC-88) 74AUP1G98_1 Product data sheet scale ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 OUTLINE VERSION IEC SOT891 Fig 20. Package outline SOT891 (XSON6) 74AUP1G98_1 Product data sheet ...
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... NXP Semiconductors 16. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 17. Revision history Table 14. Revision history Document ID Release date 74AUP1G98_1 ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 7.1 Logic configurations . . . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms ...