m35080-mn6t STMicroelectronics, m35080-mn6t Datasheet - Page 5

• Manufacturer Part Number: m35080-mn6t
• Description: 8 Kbit Serial Spi Bus Eeprom With Incremental Registers
• Manufacturer: STMicroelectronics

Figure 5. Read EEPROM Array Operation Sequence
Note: 1. The most significant address bits, A15-A10, are treated as Don’t Care.
The latch becomes reset by any of the following
events:
– Power on
– WRDI instruction completion
– WRSR instruction completion
– WRITE instruction completion.
As soon as the WREN or WRDI instruction is re-
ceived, the memory device first executes the in-
struction, then enters a wait mode until the device
is deselected.
Read Status Register (RDSR)
The RDSR instruction allows the status register to
be read, and can be sent at any time, even during
a Write operation. Indeed, when a Write is in
progress, it is recommended that the value of the
Write-In-Progress (WIP) bit be checked. The value
in the WIP bit (whose position in the status register
is shown in Table 4) can be continuously polled,
before sending a new WRITE instruction. This can
be performed in one of two ways:
Table 6. Memory Mapping
Repeated RDSR instructions (each one
consisting of S being taken low, C being clocked
8 times for the instruction and 8 times for the
read operation, and S being taken high)
020h-3FFh
000h-01Fh
Address
S
C
D
Q
0
1
HIGH IMPEDANCE
INSTRUCTION
Incremental area: a word (2 bytes) can be written only if the new value to write is larger
than the value already stored
No specific protection except the one as of Table 7
2
3
4
5
6
7
15
8
14 13
9 10
16 BIT ADDRESS
The Write-In-Process (WIP) bit is read-only, and
indicates whether the memory is busy with a Write
operation. A ’1’ indicates that a write is in progress,
and a ’0’ that no write is in progress.
The Write Enable Latch (WEL) bit indicates the
status of the write enable latch. It, too, is read-only.
Its value can only be changed by one of the events
listed earlier, or as a result of executing WREN or
WRDI instruction. It cannot be changed using a
WRSR instruction. A ’1’ indicates that the latch is
set (the forthcoming Write instruction will be exe-
cuted), and a ’0’ that it is reset (and any forthcom-
ing Write instructions will be ignored).
The Block Protect (BP0 and BP1) bits indicate the
amount of the memory that is to be write-protect-
ed. These two bits are non-volatile. They are set
using a WRSR instruction.
During a Write operation (whether it be to the
memory area or to the status register), all bits of
the status register remain valid, and can be read
using the RDSR instruction. However, during a
Write operation, the values of the non-volatile bits
3
20 21 22 23 24 25 26 27
A single, prolonged RDSR instruction
(consisting of S being taken low, C being
clocked 8 times for the instruction and kept
running for repeated read operations), as
shown in Figure 6.
2
Protection
1
0
MSB
7
6
5
DATA OUT
4
3
28 29 30
2
1
0
AI01793
M35080
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