cx24118a NXP Semiconductors, cx24118a Datasheet - Page 21

• Manufacturer Part Number: cx24118a
• Description: Advanced Modulation Digital Satellite Tuner
• Manufacturer: NXP Semiconductors

NXP Semiconductors
CX24118A_N_2
Product data sheet
During Channel Change
3.
1.
2.
3.
4.
5.
d.
There are other registers not directly related to tuning system initialization that must also
be programmed. These values are not discussed here.
Choose the appropriate dividers using register bits LODivSel (0x18[6]) and PLLRefDiv
(0x02[1])). For more detail, see
Select the gain settings. The minimum signal level settings can be used at this point.
Set the bandwidths of the baseband filters using register fields BBFil1BW[1:0] and
BBFil2BW[1:0] based on the symbol rate, roll-off, and desired carrier acquisition range.
Program the PLL dividers PLLIntDiv[8:0] and PLLFracDiv[17:0] using the values
generated from the procedure given in
follows:
a.
b.
Monitor PLL lock using register bit TUNLD. When lock has been achieved, measure the
power to determine the appropriate gain settings. Set new gain settings if required. See
Section 2.3
a.
Set register field CPLevel4[1:0] (0x11[1:0]) to 00b.
Program registers 0x19-0x1B.
Program the remaining PLL dividers into register 0x1C while setting the start bit
After lock, the charge pump values are automatically selected, based on the VCO
TUNReset (0x1C[4]) to 1.
tuning voltage and the charge pump initialization values.
for more detail.
Rev. 02 — 8 September 2009
Section 2.4
Section
2.4, and start the tuning process as
Chapter 2: Functional Descriptions
CX24118A
© NXP B.V. 2009. All rights reserved.
21