sc1189 Semtech Corporation, sc1189 Datasheet - Page 10

• Manufacturer Part Number: sc1189
• Description: Sc1189 Programmable Synchronous Dc/dc Converter, Dual Ldo Controller
• Manufacturer: Semtech Corporation

sider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be:
Using 1.5X Room temp R
BO
BOTT TT TT TT TTOM FET
BO
to conduction. The body diode is forced into conduction at
the beginning and end of the bottom switch conduction
period, so when the FET turns on and off, there is very
little voltage across it, resulting in low switching losses.
Conduction losses for the FET can be determined by:
For the example above:
Each of the package types has a characteristic thermal
impedance. For the surface mount packages on double
sided FR4, 2 oz printed circuit board material, thermal
impedances of 40
SO-8 are readily achievable. The corresponding tempera-
ture rise is detailed below:
It is apparent that single SO-8 Si4410 are not adequate
for this application, but by using parallel pairs in each
position, power dissipation will be approximately halved
and temperature rise reduced by a factor of 4.
BO
BO
P
POWER MANAGEMENT
Component Selection (Cont.)
F
R I
R I
S
F
R I
R I
S
F
R I
R I
S
COND
E
E
E
2007 Semtech Corp.
4 i
4 i
4 i
L
L
L
L
L
L
T
T
T
4
4
4
3
2
3
2
3
2
OM FET
OM FET
OM FET
OM FET - Bottom FET losses are almost entirely due
1
1
1
4
2
4
2
4
2
y t
y t
y t
0
0
0
0
0
0
0
0
0
p
p
p
I
2
3
2
3
2
3
2
O
e
e
e
5
5
5
R
DS
(
on
R
1
1
R
1
1
2
2
)
5
0
5
0
0
0
D
D
S
5 .
S
5 .
1 (
o
o (
o (
C/W for the D
) n
) n
6
1
T
T
4
8
(
(
e
o
7
7
m
m
)
0
m
p
6 .
6 .
8 .
p
DS(ON)
F
)
)
e
E
a r
T
u t
to allow for temperature rise.
P
1
1
P
1
1
2
0
e r
6 .
1 .
3 .
7 .
D
2 .
D
9 .
(
9
9
(
3
7
2
6
3
R
W
W
PAK and 80
s i
)
)
e
(
O
B
5
3
1
) C
4
3
7
t o
1
2 .
2 .
o t
6 .
P
D
D
P
D
D
S
S
m
a
a
o
2
2
0
2
2
0
C/W for the
P
P
P
P
k c
k c
8 -
8 -
F
k a
k a
a
a
E
a
a
k
k
T
g
g
e
e
10
INPUT CAP
INPUT CAP
G G G G G A A A A A TE RESIS
CURRENT SENSE, LIMIT
CURRENT SENSE, LIMIT
INPUT CAP
INPUT CAP
INPUT CAPA A A A A CIT
input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may be restrictions
on input di/dt. These restrictions require useable energy
storage within the converter circuitry, either as extra
output capacitance or, more usually, additional input ca-
pacitors. Choosing low ESR input capacitors will help maxi-
mize ripple rating for a given size.
top and bottom switching FETs limit the peak gate current
and hence control the transition time. It is important to
control the off time transition of the top FET, it should be
fast to limit switching losses, but not so fast as to cause
excessive phase node oscillation below ground as this can
lead to current injection in the IC substrate and erratic
behaviour or latchup. The actual value should be deter-
mined in the application, with the final layout and FETs.
CURRENT SENSE, LIMIT
CURRENT SENSE, LIMIT
CURRENT SENSE, LIMIT, DR
The converter is protected and it’s loadline shaped by the
signals generated from the sense resistor and associated
components.
Current Limit is given by
I
At no load the output voltage is given by:
V
so the offset is:
V
and the droop is calculated as:
V
where R
For a full design procedure for droop and offset, see Appli-
cation Note AN97-9, “Using Droop and Vout Offset for im-
proved transient response”.
OLIM
O
OS
D
=V
=Io*R
TE RESIS
TE RESIS
TE RESIST T T T T OR SELECTION
TE RESIS
=V
= V
O(nom)
O(nom)
INDUCTOR
CS
S
S
*(1+(Ra.Rb)/(Rc*(Ra+Rb))
*Rb/(Ra+Rb)
VOSENSE
.(R
is in m , V
*1000*(Ra.Rb)/(Rc*(Ra+Rb))
Current Limit, Droop and Offset circuit
V
CIT
CIT
CIT
CITORS
D
CS
+R
OR SELECTION
OR SELECTION
OR SELECTION
OR SELECTION - The gate resistors for the
ORS
ORS
ORS - since the RMS ripple current in the
ORS
F
)/(R
CURRENT LIMIT CIRCUIT
Ra
S
R
OS
.R
D
and V
F
R
)
S
Rc
, DR
, DR
, DR
, DROOP AND OFFSET
AND
OFFSET
DROOP
CIRCUIT
R
Rb
D
F
in mV
OOP AND OFFSET
OOP AND OFFSET
OOP AND OFFSET
OOP AND OFFSET
+
Vo
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SC1189
Rload
Io