z87001 ZiLOG Semiconductor, z87001 Datasheet - Page 23

• Manufacturer Part Number: z87001
• Description: Romless Spread Spectrum Cordless Phone Controller
• Manufacturer: ZiLOG Semiconductor

FUNCTIONAL DESCRIPTION (Continued)
Z87001/Z87L01
ROMless Spread Spectrum Cordless Phone Controller
The DSP core is characterized by an efficient hardware ar-
chitecture that allows fast arithmetic operations such as
multiplication, addition, subtraction and multiply-accumu-
late of two 16-bit operands. Most instructions are executed
in one clock cycle.
The DSP core is operated at the internal speed of 8.192
MHz. It has an internal RAM memory of 512 16-bit words
divided in two banks. Six register pointers provide circular
buffering capabilities and dual operand fetching. Three
vectored interrupts are complemented by a six-level stack.
One interrupt is used by the transceiver, while the two re-
maining vectors are mapped into port P1. In the phone
system, one of these interrupts is customarily reserved for
the Z87010 ADPCM Processor. The other interrupt can be
used for custom purposes.
The Z87001 may access up to 64K 16 bit words of external
ROM including 4 words for interrupt and reset vectors. The
ROM is mapped at addresses 0000h to 3FFFh, as shown
in Figure 13.
Two 16-Bit General-Purpose I/O Ports
Two 16-bit general-purpose I/O ports are directly accessi-
ble by the DSP core. These input and output pins are typ-
ically used for:
23
3FFFh
0000h
Implementation of the phone’s user interface (keypad,
LED, optional display, etc.)
Control of phone line interface (on/off hook, ring detect)
64K
USER ROM
(EXTERNAL)
Figure 4. ROM Mapping
Int. Vector 2
Reset Vector
Int. Vector 0
Int. Vector 1
3FFEh
3FFDh
3FFCh
P R E L I M I N A R Y
3FFFh
Z87010 Interface
In addition to providing clock signals to the Z87010 proces-
sor, the Z87001 interfaces to the Z87010 through two dif-
ferent paths:
The command/status interface consists of two dual-port
registers accessible by both Z87001 and Z87010 DSP
core processors. On the Z87001 side, the registers are
mapped into the DSP core processor’s register interface.
To allow access by the Z87010, the internal command/sta-
tus registers can also be decoded on the pinto of the
Z87001. Arbitration logic resolves access contentions.
The data interface allows the Z87010 processor direct ac-
cess to the Z87001’s receive and transmit rate buffers. The
rate buffers are decoded on the pin to of the Z87001, and
dedicated voice processor interface logic handles the ad-
dressing within the rate buffers.
The physical interface between Z87001 and Z87010 con-
sists of an 8-bit data bus, a 3-bit address bus and control
signals, as summarized in the following:
This bus is controlled by the Z87010. Although in the sys-
tem the Z87010 is enslaved to the Z87001 master, at the
physical level the Z87001 acts as a peripheral of the
Z87010.
The mapping of the command status and data interfaces
from the Z87010 side is given below.
Transmit
rate buffer
Receive
rate buffer
Command
Status
Interface
Control of battery charging and detection of low battery
conditions
Implementation of additional features for customizing of
the phone
A command/status interface
A data interface
VXDATA[7.0]
VXADD[2.0]
VXSTRB
VXRDYB
VXRWB
(VXADD [2.0])
Address
1
1
0
0
/Write
Read
Read/Write Control
W
W
R
R
Read Control
Address bus
Data Strobe
Data bus
----3210
----3210
76543210
76543210
(VXDATA[7.0])
DS96WRL0800
Data
Zilog