z87001 ZiLOG Semiconductor, z87001 Datasheet - Page 14
z87001
Manufacturer Part Number
z87001
Description
Romless Spread Spectrum Cordless Phone Controller
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z87001.pdf
(51 pages)
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Z87001/Z87L01
ROMless Spread Spectrum Cordless Phone Controller
ADPCM Processor Interface
The Z87001 is a peripheral device for the ADPCM Proces-
sor. The interface from the Z87001 perspective is com-
posed of an input address bus, a bidirectional data bus,
strobe and read/write input control signals and a
ready/wait output control signal.
Notes:
14
1. Requires wait state on ADPCM Processor read cycles
2. Requires no write cycle directly following read cycle on ADPCM Processor
No.
10
11
12
13
14
15
16
8
9
Signal Name
VXDATA[7..0]
VXADD[2..0]
VXSTRB
VXRDYB
VXRWB
Symbol
TaDrRY
TsDwS
ThDwS
TdSRY
ThDrS
TaDrS
ThSA
TsAS
TwS
Address, Read/Write setup time before Strobe falls
Address, Read/Write hold time after Strobe rises
Data read access time after Strobe falls
Data read hold time after Strobe rises
Strobe pulse width
Data write setup time before Strobe rises
Data write hold time after Strobe rises
Data read valid before Ready falls
Strobe high after Ready falls
Read/Write Control Signal
Strobe Control Signal
Ready Control Signal
Table 12. Write Cycles
Table 11. Read Cycles
Parameter
P R E L I M I N A R Y
Address Bus
Data Bus
Function
READ CYCLES refer to data transfers from the Z87001 to
the ADPCM Processor.
WRITE CYCLES refer to data transfers from the ADPCM
Processor to the Z87001.
Min
8.5
10
20
10
22
3
3
0
ADPCM Proc. to Z87001
ADPCM Proc. to Z87001
ADPCM Proc. to Z87001
Z87001 to ADPCM Proc.
Bidirectional
Direction
30 (1)
40 (2)
Max
DS96WRL0800
Units
ns
ns
ns
ns
ns
ns
ns
ns
Zilog
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