clc432 National Semiconductor Corporation, clc432 Datasheet - Page 11

• Manufacturer Part Number: clc432
• Description: Dual Wideband Monolithic Op Amp With Disable
• Manufacturer: National Semiconductor Corporation

Application Division
by the input resistor R
calculation as a part of the non-inverting gain equation.
Application note OA-7 gives several circuits for DC offset
correction.
Layout Considerations
It is recommended that the decoupling capacitors (0.1µF
ceramic and 6.8µF electrolytic) should be placed as close as
possible to the power supply pins to insure a proper
high-frequency low impedance bypass. Careful attention to
circuit board layout is also necessary for best performance.
Of particular importance is the control of parasitic
capacitances (to ground) at the output and inverting input
pins. See CLC431/CLC432 Evaluation Board literature for
more information.
Applications Circuit
2:1 Video Mux (CLC431)
The optional 1k
output of the 2:1 mux to the negative power supply (−V
results in improved differential gain and phase performance
(0.02% and 0.01˚) at PAL video levels.
Switched Gain Amplifier (CLC431)
As seen from the front page, the CLC431 can also be
configured as a switched-gain amplifier that is similar to the
2:1 mux. Configuring each of the two CLC431’s amplifiers
with different non-inverting gains and tying the two inputs
together (eliminating one of the input-terminating resistors)
allows the CLC431 to switch an input signal between two
different gains.
pull-down resistor connected from the
g
must be included in the output offset
Channel 2
Channel 1
SELECT
(Continued)
75
75
R
R
g
g
634
634
CC
½CLC431
½CLC431
FIGURE 3.
)
10
3
634
634
12
11
5
R
R
13
f
NC
f
9
Figure 3 illustrates the connections necessary to configure
the CLC431 as a 2:1 multiplexer in a 75 . Each of the two
CLC431’s amplifiers is configured with a non-inverting gain
of +2V/V using 634
resistors . The feedback resistor value is lower than that
recommended in order to compensate for the reduction of
loop-gain that results from the inclusion of the 50
(R
the output of the active channel from the impedance of
inactive channel yet does not affect the low output
impedance channel. Notice that for proper operation V
1(pin 13) is grounded and V
The pins associated with the disable feature are to be
connected as follows: DIS1 and DIS2 (pins 3 & 10) are
connected together as well as DIS2 and DIS1 (pins 5 & 12).
Channel 1 is selected with the application of a logic “low” to
SELECT while a logic “high” selects Channel 2.
Inactive Channel Impedances (CLC431)
The impedance that is seen when looking into the output of
a disabled CLC431 is typically represented as 1M \16pF.
The inverting input impedance becomes very high,
essentially open. Therefore, the impedance presented by a
disabled channel is (R
illustrated in Figure 4 . Its should also be noted that any trace
capacitance that is associated with the common output
connection will add in parallel to that presented by the
CLC431’s inactive channel.
j
) in the feedback loop. The 50 resistor serves to insolate
50
50
R
R
i
i
-15V
1k
75
Optional
R
75
s
feedback (R
f
+ R
DS012712-30
R
RTTL
L
V
g
out
)\ (R
2 (pin 9) is unconnected.
f
) and gain-setting (R
j
+ (1M \16pF)) as
www.national.com
resistor
RTTL
g
)