clc432 National Semiconductor Corporation, clc432 Datasheet - Page 10

• Manufacturer Part Number: clc432
• Description: Dual Wideband Monolithic Op Amp With Disable
• Manufacturer: National Semiconductor Corporation

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Application Division
The disable feature of the CLC431 is such that DIS and DIS
have common-mode input voltage ranges of (+V
(−V
temperature range. Internal clamps (not shown) protect the
DIS input from excessive input voltages that could otherwise
Figure 2 illustrates the differential mode of the CLC431’s
disable feature for ECL-type logic. In order for this mode to
operate properly, V
DIS are to be connected directly to the ECL gate as
illustrated. Applying a differential logic “high” (DIS - DIS
0.4Volts) switches the tail current of the differential pair from
Q2 to Q1 and results in the disabling of that CLC431
channel. Alternatively, applying a differential logic “low” (DIS
- DIS
pair from Q1 to Q2 and results in the enabling of that same
channel. The internal clamp, mentioned above, also protects
against excessive differential voltages up to 30 Volts while
limiting input currents to
CC
+3V) and are so guaranteed over the commercial
−0.4Volts) switches the tail current of the differential
RTTL
must be left floating while DIS and
<
3mA.
CMOS
CMOS
TTL
TTL
V
V
non-inv
non-inv
(Continued)
V
V
inv
inv
DIS
DIS
½CLC431
½CLC431
+V
+V
CC
CC
CC
) to
100k
100k
FIGURE 1.
FIGURE 2.
10
+V
+V
Q
Q
1
1
CC
CC
cause damage to the device. This condition occurs when
enough source current flows into the node so as to allow DIS
to rise to V
by 1.5Volts and guarantees that V
does not exceed 4.7Volts.
DC Performance
A current-feedback amplifier’s input stage does not have
equal nor correlated bias currents, therefore they cannot be
cancelled and each contributes to the total DC offset voltage
at the output by the following equation:
V
The input resistor R
from the non-inverting input back towards the source. For
inverting DC-offset calculations, the source resistance seen
offset
+
+
-
-
Q
Q
2
2
100k
100k
CC
I
. This clamp is activated once DIS exceeds DIS
bn
+V
+V
R
CC
CC
s
s
1
is that resistance seen when looking
R
R
g
DS012712-27
DS012712-27
f
DIS
V
DIS
V
V
V
RTTL
RTTL
out
out
V
io
DIS
1
(ground referenced)
R
R
g
f
I
bi
R
f
(1)