tda6403a NXP Semiconductors, tda6403a Datasheet - Page 3

• Manufacturer Part Number: tda6403a
• Description: 5 V Mixers/oscillators And Synthesizers For Cable Tv And Vcr 2-band Tuners
• Manufacturer: NXP Semiconductors

Philips Semiconductors
The device can be controlled according to the I
format or 3-wire bus format depending on the voltage
applied to pin SW (see Table 2). In the 3-wire bus mode
(SW = HIGH), pin LOCK/ADC is the LOCK output.
The LOCK output is LOW when the PLL loop is locked.
In the I
is set to logic 1 when the loop is locked and is read on the
SDA line (Status Byte; SB) during a READ operation in
I
(ADC) input is available on pin LOCK/ADC for digital AFC
control in the I
during a READ operation on the I
In test mode, pin LOCK/ADC is used as a TEST output for
f
(see Table 7).
When the automatic charge pump current switch mode is
activated and when the loop is phase-locked, the charge
pump current value is automatically switched to LOW. This
action is taken to improve the carrier-to-noise ratio.
The status of this feature can be read in the ACPS flag
during a READ operation on the I
Table 1 Data word length for 3-wire bus
Note
1. The selection of the reference divider is given by an automatic identification of the data word length. When the 27-bit
2000 Jan 24
2
REF
TDA6402; TDA6402A; TDA6403; TDA6403A
TDA6402; TDA6402A; TDA6403; TDA6403A
TDA6402; TDA6402A; TDA6403; TDA6403A
C-bus mode only. The Analog-to-Digital Converter
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
format is used, the reference divider is controlled by RSA and RSB bits (see Table 8). More details are given in
Chapter “PLL functional description”, Section “3-wire bus mode (SW = OPEN or V
and
2
C-bus mode (SW = LOW), the lock detector bit FL
1
2
f
DIV
2
, in both I
C-bus mode only. The ADC code is read
TYPE NUMBER
2
C-bus mode and 3-wire bus mode
2
2
C-bus (see Table 11).
C-bus (see Table 9).
2
C-bus
18-bit
19-bit
27-bit
DATA WORD
3
I
Five serial bytes (including address byte) are required to
address the device, select the VCO frequency, program
the four ports, set the charge pump current and set the
reference divider ratio. The device has four independent
I
specific voltage on input CE (see Table 6).
3-wire bus mode (SW = OPEN or VCC)
Data is transmitted to the devices during a HIGH-level on
input CE (enable line). The device is compatible with 18-bit
and 19-bit data formats, as shown in Figs 4 and 5. The first
four bits are used to program the PNP ports and the
remaining bits control the programmable divider. A 27-bit
data format may also be used to set the charge pump
current, the reference divider ratio and for test purposes
(see Fig.6).
It is not allowed to address the devices with words whose
length is different from 18, 19 or 27 bits.
2
2
C-bus mode (SW = GND)
C-bus addresses which can be selected by applying a
512
1024
programmable
REFERENCE DIVIDER
TDA6402; TDA6402A;
TDA6403; TDA6403A
CC
)”.
(1)
62.50 kHz
31.25 kHz
programmable
FREQUENCY STEP
Product specification