lm4935rlx National Semiconductor Corporation, lm4935rlx Datasheet - Page 56
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lm4935rlx
Manufacturer Part Number
lm4935rlx
Description
Audio Sub-system With Dual-mode Stereo Headphone And Mono High Efficiency Loudspeaker Amplifiers And Multi-purpose Adc
Manufacturer
National Semiconductor Corporation
Datasheet
1.LM4935RLX.pdf
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12.0 Status & Control Registers
(Continued)
12.32 DIGITAL AUDIO DATA FORMATS
I2S master mode can only be used when the DAC is enabled unless the ADC_I2S_M bit is set. PCM Master mode can only be
used when the ADC is enabled. If the PCM receiver interface is operated in slave mode the clock and sync should be enabled
at the same time as the PCM receiver uses the first PCM frame to calculate the PCM interface format. This format can not be
changed unless a soft reset is issued. It is strongly recommended that the LM4935 is operated in master mode as this eliminates
the risk of sample rate mismatch between the data converters and the audio interfaces.
In master mode the I2S_CLK has a 60/40 duty cycle and a frequency of 50*fs. In slave mode the PCM and I2S receivers only
record the 1st 16 and 18 bits of the serial words respectively. The I2S format is as follows:
20134115
2
FIGURE 10. I
S Serial Data Format (Default Mode)
20134116
FIGURE 11. PCM Serial Data Format (16 bit Slave Example)
When SAR SDO data is passed to the I2S, it is left aligned (MSB aligned) to allow lower I2S resolutions to be used.
If the DAC is driven from the PCM interface then the left channel of the DAC is used and the right channel is inactive.
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