lm4935rlx National Semiconductor Corporation, lm4935rlx Datasheet - Page 30
lm4935rlx
Manufacturer Part Number
lm4935rlx
Description
Audio Sub-system With Dual-mode Stereo Headphone And Mono High Efficiency Loudspeaker Amplifiers And Multi-purpose Adc
Manufacturer
National Semiconductor Corporation
Datasheet
1.LM4935RLX.pdf
(113 pages)
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F
12.0 Status & Control Registers
12.9 FURTHER NOTES ON PLL PROGRAMMING
The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 30 MHz with frequency errors
noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48 kHz and 44.1 kHz
sample rates from any common system clock. In systems where an isochronous I2S data stream is the source of data to the DAC
a clock synchronous to the sample rate should be used as input to the PLL (typically the I2S clock). If no isochronous source is
available then the PLL can be used to obtain a clock that is accurate to within 1 Hz of the correct sample rate although this is
highly unlikely to be a problem.
11.2896
in
12.288
19.44
19.68
19.44
19.68
14.4
16.2
16.8
19.2
19.8
14.4
16.2
16.8
19.2
19.8
13
12
13
(MHz)
11
11
F
s
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
(kHz)
48
48
48
48
48
48
48
48
48
48
TABLE 10. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates
11
13
27
14
13
27
21
17
11
13
12
17
16
14
21
11
M
4
9
8
5
9
19.53125
64.03125
22.96875
55.78125
39.0625
45.9375
45.9375
39.6875
47.0625
40.625
55.125
55.125
30.625
30.625
37.5
51.5
100
100
60
60
50
N
FIGURE 7. PLL Overview
P
5
5
5
5
5
5
5
6
5
5
5
5
5
5
5
5
5
5
5
4
5
(Continued)
PLL_M
10
12
26
13
12
26
20
16
10
12
11
16
15
13
20
10
3
8
7
4
8
30
PLL_N
100
100
60
19
60
37
50
40
64
51
55
39
22
55
45
30
45
39
47
30
9
PLL_N_MOD
204
17
16
20
16
31
30
20
25
30
22
0
0
0
0
0
1
4
2
4
2
PLL_P
4
4
4
4
4
4
4
5
4
4
4
4
4
4
4
4
4
4
4
3
4
20134111
F
out
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
12
12
12
12
12
12
12
12
12
12
(MHz)
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