mk5025q-1002 STMicroelectronics, mk5025q-1002 Datasheet - Page 35

• Manufacturer Part Number: mk5025q-1002
• Description: High Speed Link Level Controller
• Manufacturer: STMicroelectronics

4.2.9 Error Counters Seven locations in the Initialization buffer are reserved for use as error counters
which the MK50H25 will increment. These counters are intended for use by the host CPU for statistical
analysis. The MK50H25 will only increment the counters; it is up to the user to clear and preset them.
The error counters are:
4.3 Receive and Transmit Descriptor Rings
Each descriptor ring in memory is a 4 word entry. The following is the format of the receive and transmit
descriptors.
4.3.1 Receive Message Descriptor Entry
4.3.1.1 Receive Message Descriptor 0 (RMD0)
Memory Address
IADR + 44
IADR + 46
IADR + 48
IADR + 50
IADR + 52
IADR + 54
IADR + 56
IADR + 58 thru IADR + 60
BIT
15
14
13
12
NAME
OWNA
OWNB
SLF
ELF
1
5
O
W
N
A
1
4
O
W
N
B
1
3
S
L
F
Bad Frames Received
- Bad FCS
- Non-Octet Aligned
Number of FRMR frames received.
Number of T1 timeouts.
Number of REJ frames received.
Number of REJ frames transmitted.
Frames shorter than minimum length received.
Number of Aborted frames received. Enabled only if FCSER = 1
Reserved. Must be programmed as zeroes only if EIBEN = 1.
DESCRIPTION
When this bit is a zero either the HOST or the I/O ACCELERATION
PROCESSOR owns this descriptor. When this bit is a one the
MK50H25 owns this descriptor. The chip clears the OWNA bit af-
ter filling the buffer pointed to by the descriptor entry provided a valid
frame has been received. The Host sets the OWNA bit after emp-
tying the buffer. Once the MK50H25, Host, or I/O acceleration
processor has relinquished ownership of a buffer, it may not change
any field in the four words that comprise the descriptor entry.
This bit determines whether the HOST or a Slave Processor or Process
owns the buffer when OWNA is a zero.
this bit.
Start of Long Frame indicates that this is the first buffer used by the
MK50H25 for this frame. It is used for data chaining buffers. SLF is
set by the MK50H25. NOTE: A ”Long Frame” is any frame which
needs chaining.
End of Long Frame indicates that this the last buffer used by MK50H25
for this frame. It is used for data chaining buffers. If both SLF and ELF
were set, the frame would fit into one buffer and no data chaining
would be required. ELF is set by the MK50H25.
Error Counter
1
2
E
L
F
1
1
U
R
I
1
0
F
R
M
R
R
0
9
R
A
D
R
0
8
R
P
F
0
7
0
6
0
5
RBADR<23:16>
0
4
The MK50H25 never uses
0
3
0
2
0
1
0
0
MK50H25
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