tea1751lt NXP Semiconductors, tea1751lt Datasheet - Page 8

• Manufacturer Part Number: tea1751lt
• Description: Greenchip Iii Smps Control Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
TEA1751T_LT_1
Product data sheet
7.1.4 Fast latch reset
7.1.5 Overtemperature protection
7.2.1 t
7.2.2 Valley switching and demagnetization (PFCAUX pin)
7.2 Power factor correction circuit
In a typical application the mains can be interrupted briefly to reset the latched protection.
The PFC bus capacitor, C
reset.
Typically the PFC bus capacitor, C
level. When the latched protection is set, the clamping circuit of the VINSENSE circuit is
disabled. (see also
750 mV (typ) and after that is raised to 870 mV (typ), the latched protection is reset.
The latched protection is also reset by removing both the voltage on pin V
pin HV.
An accurate internal temperature protection is provided in the circuit. When the junction
temperature exceeds the thermal shutdown temperature, the IC stops switching. As long
as OTP is active, the capacitor C
is supplied from the HV pin if the V
OTP is a latched protection. It can be reset by removing both the voltage on pin V
on pin HV or by the fast latch reset function. (See
The power factor correction circuit operates in quasi-resonant or discontinuous conduction
mode with valley switching. The next primary stroke is only started when the previous
secondary stroke has ended and the voltage across the PFC MOSFET has reached a
minimum value. The voltage on the PFCAUX pin is used to detect transformer
demagnetization and the minimum voltage across the external PFC MOSFET switch.
The power factor correction circuit is operated in t
reduction of a typical application is well within the class-D requirements.
The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry
connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the
voltage across the PFC MOSFET. The next stroke is started if the voltage across the PFC
MOSFET is at its minimum in order to reduce switching losses and ElectroMagnetic
Interference (EMI) (valley switching).
If no demagnetization signal is detected on the PFCAUX pin, the controller generates a
zero current signal (ZCS), 50 s (typ) after the last PFCGATE signal.
If no valley signal is detected on the PFCAUX pin, the controller generates a valley signal
4 s (typ) after demagnetization was detected.
To protect the internal circuitry during lightning events, for example, it is advisable to add a
5 k series resistor to this pin. To prevent incorrect switching due to external disturbance,
the resistor should be placed close to the IC on the printed-circuit board.
on
control
Section
Rev. 01 — 10 July 2008
bus
7.2.9) As soon as the VINSENSE voltage drops below
, does not have to discharge for this latched protection to
VCC
bus
CC
is not recharged from the HV mains. The OTP circuit
, has to discharge for the V
supply voltage is not sufficient.
TEA1751T; TEA1751LT
on
Section
control. The resulting mains harmonic
GreenChip III SMPS control IC
7.1.4)
CC
to drop to this reset
© NXP B.V. 2008. All rights reserved.
CC
and on
CC
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and