adg849 Analog Devices, Inc., adg849 Datasheet - Page 6

• Manufacturer Part Number: adg849
• Description: 3 V/5 V Cmos 0.5 ? Spdt/2 1 Mux In Sc70
• Manufacturer: Analog Devices, Inc.

ADG849
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Terminology
Mnemonic
V
GND
I
S
D
IN
R
∆R
R
I
I
V
V
V
I
C
C
t
t
t
Charge
Injection
Crosstalk
Off Isolation
Bandwidth
On-Response
Insertion Loss
THD + N
DD
S
D
INL
ON
OFF
BBM
ON
FLAT(ON)
DD
D
INL
INH
S
D
, I
(Off )
, C
ON
(Off )
(V
S
(I
(On)
INH
S
S
)
(On)
)
Function
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Positive Supply Current.
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input.
Ohmic Resistance between D and S.
On-Resistance Match Between any Two Channels i.e., R
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the
specified analog signal range.
Source Leakage Current with the Switch Off.
Channel Leakage Current with the Switch On.
Analog Voltage on Terminals D, S.
Maximum Input Voltage for Logic 0.
Minimum Input Voltage for Logic 1.
Input Current of the Digital Input.
Off Switch Source Capacitance. Measured with reference to ground.
On Switch Capacitance. Measured with reference to ground.
Delay time between the 50% and 90% points of the digital input and switch on condition.
Delay time between the 50% and 90% points of the digital input and switch off condition.
On or off time measured between the 80% points of both switches when switching from one to another.
A measure of the glitch impulse transfered from the digital input to the analog output during switching.
A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance.
A measure of unwanted signal coupling through an off switch.
The frequency at which the output is attenuated by 3 dB.
The frequency response of the on switch.
The loss due to the on-resistance of the switch.
The ratio of harmonic amplitudes plus the noise of a signal to the fundamental.
GND
V
DD
Figure 2. Pin Configuration
IN
Rev. 0| Page 6 of 12
1
2
3
(Not to Scale)
ADG849
TOP VIEW
ON
6
5
4
Maximum to R
S2
D
S1
ON
Minimum.