cbtl03sb212 NXP Semiconductors, cbtl03sb212 Datasheet - Page 4

• Manufacturer Part Number: cbtl03sb212
• Description: Cbtl03sb212 Displayport Gen2 Sideband Signal Multiplexer
• Manufacturer: NXP Semiconductors

NXP Semiconductors
CBTL03SB212
Product data sheet
6.2 Pin description
Table 2.
[1]
Symbol
SEL
XSD_N
AUX+
AUX−
DDC_CLK
DDC_DAT
HPD
AUX1+
AUX1−
AUX2+
AUX2−
DDC_CLK1
DDC_DAT1
DDC_CLK2
DDC_DAT2
HPD_1
HPD_2
V
GND
DD
HVQFN20 package die supply ground is connected to both GND pin and exposed center pad. GND pin and
the exposed center pad must be connected to supply ground for proper device operation. For enhanced
thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using
a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the printed-circuit board in the thermal pad region.
[1]
Pin description
Pin
5
15
20
1
2
3
4
17
16
14
13
12
11
9
8
10
7
6, 18
19
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 February 2011
differential I/O
single-ended I/O
Type
3.3 V CMOS
single-ended input
3.3 V CMOS
single-ended input
differential I/O
differential I/O
differential I/O
single-ended I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
single-ended I/O
power supply
ground
DisplayPort Gen2 sideband signal multiplexer
Description
Selects between two multiplexer/switch paths.
Shutdown pin. Should be driven HIGH or
connected to V
LOW, all paths are switched off (non-conducting
high-impedance state), and supply current
consumption is minimized.
High-speed differential pair for AUX signals,
right-side.
Pair of single-ended terminals for DDC clock and
data signals, right-side.
Single-ended channel for the HPD signal,
right-side.
High-speed differential pair for AUX signals, path 1,
left-side.
High-speed differential pair for AUX signals, path 2,
left-side.
Pair of single-ended terminals for DDC clock and
data signals, path 1, left-side.
Pair of single-ended terminals for DDC clock and
data signals, path 2, left-side.
Single-ended channel for the HPD signal, path 1,
left-side.
Single-ended channel for the HPD signal, path 2,
left-side.
3.3 V power supply.
Ground.
DD
CBTL03SB212
for normal operation. When
© NXP B.V. 2011. All rights reserved.
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