cbtl06dp211 NXP Semiconductors, cbtl06dp211 Datasheet
cbtl06dp211
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cbtl06dp211 Summary of contents
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... It is designed for delivering optimum performance at DP data rates of 1.62 Gbit/s and 2.7 Gbit/s. A typical application of CBTL06DP211 is on motherboards where one of two GPU display sources needs to be selected to connect to a display sink device or connector. A controller chip selects which path to use by setting a select signal HIGH or LOW. Due to the non-directional nature of the signal paths (which use high-bandwidth pass-gate technology), the CBTL06DP211 can also be used in the reverse topology, e ...
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... Package Name Description TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; body 5 × 5 × 0.8 mm All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 CBTL06DP211 DisplayPort Gen1 multiplexer Version SOT918-1 [1] © NXP B.V. 2011. All rights reserved ...
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... HPD_1 1 HPD_2 GPU_SEL DDC_AUX_SEL TST0 XSD Functional diagram All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 CBTL06DP211 DisplayPort Gen1 multiplexer VDD 4 OUT_n+ OUT_n− AUX+ or DDC clock AUX+ AUX− AUX− or DDC data HPDIN GND 002aag002 © ...
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... OUT_2+ OUT_3+ TST0 AUX+ HPD_2 GND HPD_1 VDD Transparent top view Ball mapping All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 CBTL06DP211 DisplayPort Gen1 multiplexer CBTL06DP211EE 002aag003 Transparent top view IN1_1− ...
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... High-speed differential pair for AUX signals, path 1, left-side. High-speed differential pair for AUX signals, path 2, left-side. All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 CBTL06DP211 DisplayPort Gen1 multiplexer © NXP B.V. 2011. All rights reserved ...
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... H7 7. Functional description Refer to The CBTL06DP211 uses a 3.3 V power supply. All main signal paths are implemented using high-bandwidth pass-gate technology and are non-directional. No clock or reset signal is needed for the multiplexer to function. The switch position for the main channels is selected using the select signal GPU_SEL. ...
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... Shutdown function The CBTL06DP211 provides a shutdown function to minimize power consumption when the application is not active but power to the CBTL06DP211 is provided. Pin XSD (active LOW) puts all channels in off mode (non-conducting high-impedance state) while reducing current consumption to near-zero. Table 6. XSD 0 ...
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... CMOS inputs HPD, DDC/AUX inputs other inputs ambient temperature operating in free air Section 11.1 “Special considerations”. Section 11.1 “Special All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 CBTL06DP211 DisplayPort Gen1 multiplexer Min Max −0.3 +5 −40 +85 [1] - ...
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... Hz ≤ f ≤ 1.5 GHz adjacent channels are on ≤ f ≤ 1.5 GHz −3.0 dB intercept from left-side port to right-side port or vice versa intra-pair inter-pair All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 CBTL06DP211 DisplayPort Gen1 multiplexer Min Typ = ...
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... AUX from left-side port to right-side port or vice versa Conditions no load from HPDIN to HPD_x or vice versa Conditions = 3.6 V; 0.3 V ≤ All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 CBTL06DP211 DisplayPort Gen1 multiplexer Min Typ Max −0 ...
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... Certain cable or dongle misplug scenarios make it possible for input condition to occur on pins AUX+ and AUX−, as well as HPDIN. When AUX+ and AUX− are connected through a minimum of 2.2 kΩ resistor each, the CBTL06DP211 will sink current but will not be damaged. Similarly, HPDIN may be connected via at least a 1 kΩ resistor. ...
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... 5.1 5.1 0 0.15 4.9 4.9 REFERENCES JEDEC JEITA MO-195 - - - All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 CBTL06DP211 DisplayPort Gen1 multiplexer detail 0.05 0.08 0.1 EUROPEAN PROJECTION SOT918-1 y ...
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... Solder bath specifications, including temperature and impurities CBTL06DP211 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 CBTL06DP211 DisplayPort Gen1 multiplexer © NXP B.V. 2011. All rights reserved ...
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... Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 5. All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 CBTL06DP211 DisplayPort Gen1 multiplexer Figure 5) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 ...
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... ESD HBM HDMI HPD I/O 15. Revision history Table 17. Revision history Document ID Release date CBTL06DP211 v.1 20110221 CBTL06DP211 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level Temperature profiles for large and small components ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 CBTL06DP211 DisplayPort Gen1 multiplexer © NXP B.V. 2011. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 1 — 21 February 2011 CBTL06DP211 DisplayPort Gen1 multiplexer © NXP B.V. 2011. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 21 February 2011 Document identifier: CBTL06DP211 ...