adg796a Analog Devices, Inc., adg796a Datasheet - Page 17

• Manufacturer Part Number: adg796a
• Description: I2c-compatible, Wide Bandwidth, Hex 2 1 Multiplexer
• Manufacturer: Analog Devices, Inc.

THEORY OF OPERATION
The ADG796A is a monolithic CMOS device comprising six 2:1
multiplexer/demultiplexers controllable via a standard I
interface. The CMOS process provides ultralow power
dissipation, yet offers high switching speed and low on resistance.
The on resistance profile is very flat over the full analog input
range, and wide bandwidth ensures excellent linearity and low
distortion. These features, combined with a wide input signal
range, make the ADG796A the ideal switching solution for a
wide range of TV applications.
The switches conduct equally well in both directions when on.
In the off condition, signal levels up to the supplies are blocked.
The integrated serial I
multiplexers.
The ADG796A has many attractive features, such as the ability
to individually control each multiplexer and the option of
reading back the status of any switch through the I
The following sections describe these features in more detail.
I
The ADG796A is controlled via an I
interface (refer to the I
Philips Semiconductor) that allows the part to operate as a slave
device (no clock is generated by the ADG796A). The communi-
cation protocol between the I
as follows:
1.
2.
SDA
NOTES
1. X = LOGIC STATE DOES NOT MATTER.
SCL
2
C SERIAL INTERFACE
BY MASTER
CONDITION
START
The master initiates data transfer by establishing a start
condition defined as a high-to-low transition on the SDA
line while SCL is high. This indicates that an address/data
stream follows. All slave devices connected to the bus
respond to the start condition and shift in the next eight
bits, consisting of a seven bit address (MSB first) plus an
R/ W bit. This bit determines the direction of the data flow
during the communication between the master and the
addressed slave device.
The slave device whose address corresponds to the
transmitted address responds by pulling the SDA line low
during the ninth clock pulse (this is called the acknowledge
bit). At this stage, all other devices on the bus remain idle
while the selected device waits for data to be written to, or
ADDRESS BYTE
2
2
C interface controls the operation of the
C-Bus Specification available from
2
C master and the device operates
A1
A0
2
C-compatible serial bus
ACKNOWLEDGE
BY SWITCH
R/W
AX7
2
C interface.
AX6
2
AX5 AX4 AX3 AX2 AX1 AX0
C serial
Figure 27. Write Operation
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3.
4.
I
The ADG796A has a seven-bit I
significant bits are internally hardwired while the last two bits,
A0 and A1, are user adjustable. This allows the user to connect
up to four ADG796As to the same bus. The I
the configuration of the seven-bit address.
Seven-Bit I
MSB
1
WRITE OPERATION
When writing to the ADG796A, the user must begin with an
address byte and R/ W bit. Next, the switch acknowledges that it
is prepared to receive data by pulling SDA low. Data is loaded
into the device as a 16-bit word under the control of a serial clock
input, SCL. Figure 27 illustrates the entire write sequence for
the ADG796A. The first data byte (AX7 to AX0) controls the
status of the switches, while the LDSW and RESETB bits from
the second byte control the operation mode of the device.
2
C ADDRESS
ACKNOWLEDGE
read from, its serial register. If the R/ W bit is set high, the
master reads from the slave device. However, if the R/ W bit
is set low, the master writes to the slave device.
Data transmits over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of the clock signal (SCL) and remain stable
during the high period (SCL). This is because a low-to-
high transition when the clock signal is high can be
interpreted as a stop event, which ends the communication
between the master and the addressed slave device.
After transferring all data bytes, the master establishes a
stop condition, defined as a low-to-high transition on the
SDA line while SCL is high. In write mode, the master pulls
the SDA line high during the 10
stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (the SDA line
remains high). The master then brings the SDA line low
before the 10
clock pulse to establish a stop condition.
BY SWITCH
0
2
C Address Bit Configuration
X
th
X
1
clock pulse, and then high during the 10
X
X
0
X
2
C address. The five most
X
th
RESETB
0
clock pulse to establish a
LDSW
ACKNOWLEDGE
2
C bit map shows
BY SWITCH
A1
ADG796A
BY MASTER
CONDITION
STOP
LSB
A0
th