hd64338023s Renesas Electronics Corporation., hd64338023s Datasheet - Page 389

• Manufacturer Part Number: hd64338023s
• Description: Renesas 8-bit Single-chip Microcomputer Super Low Power Series
• Manufacturer: Renesas Electronics Corporation.

Bit 2—Transmit End (TEND)
Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent.
Bit 2 is a read-only bit and cannot be modified.
Bit 2
TEND
0
1
Bit 1—Multiprocessor Bit Eeceive (MPBR)
Bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in
asynchronous mode.
Bit 1 is a read-only bit and cannot be modified.
Bit 1
MPBR
0
1
Note: * When bit RE is cleared to 0 in SCR3 with the multiprocessor format, bit MPBR is not
Bit 0—Multiprocessor Bit Transfer (MPBT)
Bit 0 stores the multiprocessor bit added to transmit data when transmitting in asynchronous
mode. The bit MPBT setting is invalid when synchronous mode is selected, when the
multiprocessor communication function is disabled, and when not transmitting.
Bit 0
MPBT
0
1
affected and retains its previous state.
Description
Transmission in progress
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
Transmission ended
Setting conditions:
When bit TE in SCR3 is cleared to 0
When bit TDRE is set to 1 when the last bit of a transmit character is sent
Description
Data in which the multiprocessor bit is 0 has been received *
Data in which the multiprocessor bit is 1 has been received
Description
A 0 multiprocessor bit is transmitted
A 1 multiprocessor bit is transmitted
Section 10 Serial Communication Interface
Rev. 7.00 Mar 10, 2005 page 347 of 652
REJ09B0042-0700
(initial value)
(initial value)
(initial value)