hd64338023s Renesas Electronics Corporation., hd64338023s Datasheet - Page 18

• Manufacturer Part Number: hd64338023s
• Description: Renesas 8-bit Single-chip Microcomputer Super Low Power Series
• Manufacturer: Renesas Electronics Corporation.

Rev. 7.00 Mar 10, 2005 page xviii of xlii
Item
9.7.5 Application
Notes
10.2.8 Bit Rate
Register (BRR)
Table 10.3 Examples
of BRR Settings for
Various Bit Rates
(Asynchronous
Mode) (2)
Page
328
329
349
Revision (See Manual for Details)
Description amended
2. Use a clock with a frequency of up to 16 MHz for input to the
AEVH and AEVL pins, and ensure that the high and low widths
of the clock are at least half the OSC clock cycle duration. The
duty cycle is immaterial.
Description amended
Table amended
Notes amended
1. The value set in BRR is given by the following equation:
Mode
Watch, subactive, subsleep, standby
φw = 32.768 kHz or 38.4 kHz *
Note: * Does not apply to H8/38124 Group.
Bit Rate
(bit/s)
110
150
200
250
300
600
1200
2400
4800
9600
19200
31250
38400
where
N =
(32 • 2
n
3
3
3
3
3
3
3
3
3
2
2
0
0
B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
φ: System clock frequency
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.4.)
φ
10 MHz
2n
N
43
32
23
19
15
7
3
1
0
1
0
9
7
• B)
φ
Error
(%)
0.88
–1.36
1.73
–2.34
1.73
1.73
1.73
1.73
1.73
1.73
1.73
0
1.73
– 1
(φw/2)
(φw/4)
(φw/8)
Maximum AEVH/AEVL Pin Input
Clock Frequency
1000 kHz
500 kHz
250 kHz